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VCU110 IBERT GTY BullsEye Reference Clock

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Visitor
Posts: 6
Registered: ‎09-22-2016

VCU110 IBERT GTY BullsEye Reference Clock

Hello,

 

I am trying to run the VCU110 GT IBERT .zip files that I found in the Xilinx website.

 

I tried to set up all the system with the XTP380 (VCU110 Software Install and Board Setup) as well as to follow the XTP374 (VCU110 GT IBERT Design). I want to assess the connection in the Bullseye in the GTY.

 

However, I am not finding any reference to the REF CLOCK that must be used in the Bullseye while refering to this specific IBERT .bit.  In the setup pdf (XTP380) I found the following: "GTY Ref Clock to 175 MHz clock source (not included)"! May I assume that this reference clock is the one that must be used in the IBERT .bit from the .zip files? And, which specifications shall I respect? DC Offset, Peak to Peak Voltage, Sine or Square wave?

 

Best regards

Daniel Dinis

Xilinx Employee
Posts: 24
Registered: ‎06-02-2017

Re: VCU110 IBERT GTY BullsEye Reference Clock

Hi Daniel,

 

If you use the IBERT .zip files the Xilinx provided, the reference clock selected in the design is identical with the hardware setup on the board. So I think you can run the project directly.


The better way to understand ibert is following the "Create IBERT Design for GTYs" in the XTP374. The doc introduces how to generate the ibert project step by step, including how to select reference clock. You can find the clocking routing in the sch of VCU110.

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Visitor
Posts: 6
Registered: ‎09-22-2016

Re: VCU110 IBERT GTY BullsEye Reference Clock

Hello Zhiq,

Thank you so much for your speedy answer.

 

So, I can assume that the reference clock is 175 MHz? And in terms of specifications? Voltage Peak to Peak, DC Offset, Square or Sinewave? I am used to boards like VCU1287 or ML628 where I have a Programmable CLK daughter board with SMA connectors.

 

Best regards

 

Xilinx Employee
Posts: 12
Registered: ‎10-19-2011

Re: VCU110 IBERT GTY BullsEye Reference Clock

Hi Daniel,

 

yes, the refclk needs to be 175MHz. And you need to bring it in through the bullseye connector as with this line rate there is no sharing of the refclk between quads. For the clock specification please look at the datasheet ds893. You find the phase noise requirements there. But as you are used to the super clock modules, go ahead and use these. There is no module with the VCU110 itself, but you could use the other boards with their module.

 

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Xilinx Employee
Posts: 2,309
Registered: ‎02-16-2010

Re: VCU110 IBERT GTY BullsEye Reference Clock

Based on the design provided for VCU110 IBERT GTY, I find that you will need to connect the refclk pins on bulls eye connector to a clock of 175MHz.
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Visitor
Posts: 6
Registered: ‎09-22-2016

Re: VCU110 IBERT GTY BullsEye Reference Clock

Thank you so much Eschidl and Venkata,
I used the 175 MHz reference clock from the superclock-2 board (from the VCU1287) and I followed the IBERT (xtp374-vcu110-gt-ibert-es2-2015-4) tutorial (with 2015.2, 2015.4 and 2016.2). In particular, I executed the ibert_bank_gty.tcl and the ibert_bank_bullseye.tcl, but I got the same error "[Common 17-161] Invalid option value ' ' specified for 'hw_sio_rx'. Thus, even though the .bit seems to be succesffuly downloaded, I can not see any links.
I just want to assess the loopback in the bullseye GTY.
Can you please help me?
Best regards

Xilinx Employee
Posts: 2,309
Registered: ‎02-16-2010

Re: VCU110 IBERT GTY BullsEye Reference Clock

Do you find PLL is locked after loading the bitstream?

Can you try to create the links manually?
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Visitor
Posts: 6
Registered: ‎09-22-2016

Re: VCU110 IBERT GTY BullsEye Reference Clock

Hello Dear Venkata,

Unless the lock is locked to the LED, I can not understand, because after the error, I do not have any kind of information. Neither ILA, or nothing. Just the error, and the hardware manager remains empty. This also means that the manual creation of links is disabled.Any other sugestion?

Best regards

Daniel Dinis

Xilinx Employee
Posts: 12
Registered: ‎10-19-2011

Re: VCU110 IBERT GTY BullsEye Reference Clock

Hi Daniel,

 

after programming the device, do you see any debug core listed in the HW manager Hardware view?

Sounds like not.

This might then be an issue with the system clock. This needs to be present during config.

Visitor
Posts: 6
Registered: ‎09-22-2016

Re: VCU110 IBERT GTY BullsEye Reference Clock

Hello Dear Eschidl,

No, I do not have any debug core. Just the sysmon, presenting the temperature. What do you recommend me to do? I am out of ideas!

Best regards