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2,651 Views
Registered: ‎08-24-2017

VCXO replacement in GTY of Virtex ultrascale+

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Hi,

 

I am planning to use the VCXO replacement technique as described in XAPP1241 and XAPP589 on a Virtex ultrascale+ device. The bit-rate limit of the GTY for virtex ultrascale in this mode seems to be 16.375Gbps. Is this limit still present in the ultrascale+ architecture? It would be nice to run the VCXO replacement at 25G. 

 

BR

Jens

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4,248 Views
Registered: ‎09-18-2014

Re: VCXO replacement in GTY of Virtex ultrascale+

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jens_rasmussen,

 

Yes. That is still the limit, however that is not to say you cannot push it out to 25G and try it out for your self. The main issue is additional jitter that is introduced onto the system. If you and your design are able to tolerate the additional introduced jitter than it may be possible. I don't think we have any figures for the amount of additional jitter introduced but you can test that out for your self if needed. Just note the the GTH/GTY user guide states this limitation on the TXPI PPM Controller fairly clearly. If you need more guidance please please get in touch with your local Xilinx or associated Avnet FAE.  

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Moderator
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4,249 Views
Registered: ‎09-18-2014

Re: VCXO replacement in GTY of Virtex ultrascale+

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jens_rasmussen,

 

Yes. That is still the limit, however that is not to say you cannot push it out to 25G and try it out for your self. The main issue is additional jitter that is introduced onto the system. If you and your design are able to tolerate the additional introduced jitter than it may be possible. I don't think we have any figures for the amount of additional jitter introduced but you can test that out for your self if needed. Just note the the GTH/GTY user guide states this limitation on the TXPI PPM Controller fairly clearly. If you need more guidance please please get in touch with your local Xilinx or associated Avnet FAE.  

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Registered: ‎08-24-2017

Re: VCXO replacement in GTY of Virtex ultrascale+

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Ok, thank you for your answer. I have a hunch/feeling the 16.375G limit might have something to do with transceivers using both rising and falling edges of the bit-clock and this is in fact a hard limit. But I am out on a limb here...

 

/Jens

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