05-04-2018 06:34 AM
I have Virtex 7 with transceiver configured to 10G. When I plug the cable and then load the FPGA the CDR locks and I get stable and consistent data.
If I load the FPGA and then connect the cable, the CDR wouldn't lock at all, and I see AAAAA or 55555 data on the RXDATA bus.
Would could be the issue? How can i configure/reset the FPGA so that it will lock on the data?
05-04-2018 07:23 AM
For the clock recovery ( CDR) to work correctly you must have a stable input signal during the reset. It sounds like this may not be the case?
05-04-2018 07:28 AM
AAAAA or 55555 seems the effect of a DFE equalizer. are you using DFE?
you might try to use LPM mode or to reset the receiver completely (in particular the equalizer)
05-04-2018 09:40 AM
Thank you for reply. Yes, I am looking for a way to plug and unplug the cable without the need to power up the device every time. Is there a way to lock on the signal after some time?
05-04-2018 10:10 AM
The fact that data patterns switch between AAAAA and 55555 indicates that CDR is not locked, and there is occasional bit slip (one bit is either inserted or removed). If you have connected ILA, you might even see the point of the bit slip. I've seen it happening every few usec in my designs.
From my experience, Xilinx transceivers - GTX, GTH, GTY - are very picky to the reset sequence. So it might be the problem in your case. Relevant reset signals are RXCDR_RESET and global transceiver reset.
Another problem might be clock frequency difference between Rx and Tx side. Do you have identical clock driving both Rx and Tx ? If not, what's the clock drift in PPM ? Transceiver can only handle certain amount of drift before losing lock.
One thing to try is to make sure that internal loopback works before dealing with external signal source.
05-04-2018 10:20 AM
>> AAAAA or 55555 seems the effect of a DFE equalizer. are you using DFE?
>> you might try to use LPM mode or to reset the receiver completely (in particular the equalizer)
Thank you. I will try that.
05-04-2018 10:25 AM - edited 05-04-2018 10:27 AM
It would certainly work better if you put the CDR in HOLD while it is unplugged. Depending on the line rate you might be able to use RXCDR_HOLD_DURING_EIDLE, RX_DFE_LPM_HOLD_DURING IDLE or RXCDR_FR_RESET_ON_EIDLE. Page 202,181 and 192 of UG476. Ideally you would do a full RXRESET if that is possible but you don't need a power cycle.
05-08-2018 01:59 AM
basically after cable is connected, user logic should reset CDR by asserting GTRXRESET.
user logic should be able to determine the cable connection by looking for some known data patterns.
if the known data pattern has not been detected for a while, it should reset the receiver.
user logic repeated this process until the pattern is received.
from the data pattern you mentioned, AAAA or 5555, it seems like RX pin are not even driven actively by the cable.
Is the transmitter ON?
when RX pins are floated or not driven, the RXDATA would be 10101010... if DFE mode is selected.