12-31-2019 06:55 AM
Hey all, I have been working on a project for some time now where the objective was to receive 5.6GB/s of data on 6 different lines into an FPGA using the GTX/GTH transceivers on the Virtex-7 VC7215. There is a clock synchronous with the data at 2.8GHz DDR. After many months of work, I have come to the conclusion that there is absolutely no way that any FPGA can handle this as the data is unencoded, NRZ, and no internal/external memory element could receive 5.6GB/s. With that being said, can anyone discuss what the transceivers are good for in terms of receiving data if at high speeds the FPGAs can't even support it?
12-31-2019 08:09 AM
Maybe the word 'deserializer' brings some of the light you have been looking for in those months of work.
Typically, Gb transceivers are serial (one bit after other). Typically, data is deserialized and becomes a stream of 16, 32, 64, etc. bits and so the clock is divided as well.
Yes, you are right that even a fast Virtex-7 -3 speed won't run IP cores much faster than 300 MHz, but 300 MHz x 64 bits = 19.2 Gbps. Voila. Does this make sense?
12-31-2019 08:38 AM
12-31-2019 08:57 AM
01-02-2020 05:31 AM
How about ethernet?
And HDMI 2.0 (5.4 Gbps/lane), Displayport 1.4 (8.1 Gbps/lane), SMPTE-SDI...
01-09-2020 05:06 PM - edited 01-09-2020 05:08 PM
..., USB, SPI, Thunderbolt, SATA, PCIe, ...
And dozens and dozens of other protocols.
Clock/data recovery techniques are REALLY old - 8b10b encoding was developed in the 1980s.