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Observer muqsh
Observer
378 Views
Registered: ‎05-18-2018

XC7V690T GTH IBERT working LineRate Mismatch

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Systerm : Win7_64bit

Software: Vivado 2017.4

On my board, using XC7V690T FFG1158 -2, bank_117 and bank_118, with bank_118 GTREFCLK0 clock 147.456MHz.

The setting of "LineRate" is "7.3728 G", and using CPLL.

During test, it showes that, CPLL is locked, and the LineRate is "4.000 G".

Checked the parameters:
CPLL_REFCLK_DIV = 1
CPLL_FBDIV_45 = 5
CPLL_FBDIV = 2
RXOUT_DIV = 1
TXOUT_DIV = 1


It's strange that the "LineRate" is wrong.

Could someone please help me about this?

 

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Observer muqsh
Observer
277 Views
Registered: ‎05-18-2018

回复: XC7V690T GTH IBERT working LineRate Mismatch

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Problem solved!

It is cheerful!

The reason is that, both the xci and xdc should be joined up.

It must be both import_ip the IBERT*.xci and read_xdc the example_IBERT*.xdc.

Do not to manually change the properity values in the xdc file.

If you changed the XCI, it also changed the XDC.

In a word,  one XCI one XDC accordingly.

 

 

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11 Replies
Observer muqsh
Observer
353 Views
Registered: ‎05-18-2018

Re: XC7V690T GTH IBERT working LineRate Mismatch

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Using TCL command to set the CPLLs:

CPLL_REFCLK_DIV = 1

CPLL_FBDIV_45 = 5

CPLL_FBDIV = 5

RXOUT_DIV = 1

TXOUT_DIV = 1 T

 

It showes "10 Gbps".

 

According to the equations in ug476 CPLL, the input clock should be 200MHz.

But the real clock is 147.456MHz.

So, it seems something wrong in the vivado tool.

 

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Xilinx Employee
Xilinx Employee
346 Views
Registered: ‎10-19-2011

Re: XC7V690T GTH IBERT working LineRate Mismatch

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Hi @muqsh ,

please have a look at this post:

https://forums.xilinx.com/t5/Serial-Transceivers/Linerate-confusion-using-7series-VC707-IBERT/td-p/959887

Let me know if this helps.

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Observer muqsh
Observer
330 Views
Registered: ‎05-18-2018

Re: XC7V690T GTH IBERT working LineRate Mismatch

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Hi @

Thanks.

In your link page, it post the same mismatch phenomenon. 

In my design, the ibert*.xci is imported into my project. And in the .XDC file, it constraints the GTH ref clock to "147.456MHz", too.

I checked and tested, but it is not solved.

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Xilinx Employee
Xilinx Employee
324 Views
Registered: ‎08-07-2007

回复: XC7V690T GTH IBERT working LineRate Mismatch

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hi @muqsh 

 

How did you select the System Clock?

does it match the hardware?

If it is sourced by External, you can change it to Quad_xxx clock and see if it helps.

 

Thanks,

Boris

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Observer muqsh
Observer
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Registered: ‎05-18-2018

回复: XC7V690T GTH IBERT working LineRate Mismatch

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The selection of clock source is "Using QUAD clock", which is Bank_118 GTREFCLK0.
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Observer muqsh
Observer
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Registered: ‎05-18-2018

回复: XC7V690T GTH IBERT working LineRate Mismatch

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By the way, when using JESD204_RX function with the GTREFCLK=147.456MHz, LineRate=7.3728Gbps, it works OK.
The only problem is using IBERT for test, it shows wrong LineRate info, and the test FAILED.
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Xilinx Employee
Xilinx Employee
312 Views
Registered: ‎08-07-2007

回复: XC7V690T GTH IBERT working LineRate Mismatch

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hi @muqsh 

 

if possible, you can try testing with a single bank instead of two.

you can generate two bit streams for bank 118 and bank 117, respectively.

 

Thanks,

Boris

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Observer muqsh
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Registered: ‎05-18-2018

回复: XC7V690T GTH IBERT working LineRate Mismatch

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Hi @borisq
Test done.
Two bits with IBERT for bank_118 and bank_117 respectively.
Using the Bank_118_GTREFCLK0 = 147.456MHz.
Near-End PCS loopback.
Both show the Line_Rate=4.000 Gbps.
......

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Xilinx Employee
Xilinx Employee
288 Views
Registered: ‎08-07-2007

回复: XC7V690T GTH IBERT working LineRate Mismatch

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hi @muqsh 

 

what is TXUSRCLK Frequency and RXUSRCLK Frequency?

 

right click on the bar like "Loopback", a drip list will be poped. you can add TXUSRCLK Frequency and RXUSRCLK Frequency to display.

 

Thanks,

Boris

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Observer muqsh
Observer
283 Views
Registered: ‎05-18-2018

回复: XC7V690T GTH IBERT working LineRate Mismatch

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It shows about 125.000MHz.
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Observer muqsh
Observer
278 Views
Registered: ‎05-18-2018

回复: XC7V690T GTH IBERT working LineRate Mismatch

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Problem solved!

It is cheerful!

The reason is that, both the xci and xdc should be joined up.

It must be both import_ip the IBERT*.xci and read_xdc the example_IBERT*.xdc.

Do not to manually change the properity values in the xdc file.

If you changed the XCI, it also changed the XDC.

In a word,  one XCI one XDC accordingly.

 

 

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