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Registered: ‎07-23-2019

Zynq ultrascale+ GTH jitter spec?

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Is there any jitter specification for the GTH transceivers?

So far what I'm doing is select a reference oscillator with "low jitter" that the manufacturer recommends it for my application then trust the GTH will comply with the spec (10 GbE), and of course having proper low noise supplies, bypass, etc.

Is there a way to show someone else something more objective than this "trust me, it will work"?

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Registered: ‎01-22-2015

Re: Zynq ultrascale+ GTH jitter spec?

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@archangel-lightworks 

Table 102 of the datasheet, DS925(v1.16), indirectly gives the jitter specification for the GTH transceiver clock.  That is, Table 102 gives a phase noise mask/envelope for the clock frequency spectra.

According to AR#63026, the phase noise mask is a preferred method for specifying jitter of the UltraScale GTH/GTY reference clock. 

The websites listed below have calculators that help you convert the phase noise mask into traditional time-measurements of jitter.

https://www.silabs.com/jittercalculator/phase-noise-jitter-calculator.aspx 

https://abracon.com/phaseNoiseCalculator.php

https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3359.html

The phase noise mask/envelope is well understood by manufacturers of quality clock oscillators.  So, when buying a clock oscillator for your project, give them a phase noise mask specification rather than a jitter(time) specification.  

Finally, if you are buffering the clock before sending it to the FPGA, then include the "added jitter" specification of the buffer in your total budget for GTH clock jitter.

Mark

 

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475 Views
Registered: ‎01-22-2015

Re: Zynq ultrascale+ GTH jitter spec?

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@archangel-lightworks 

Table 102 of the datasheet, DS925(v1.16), indirectly gives the jitter specification for the GTH transceiver clock.  That is, Table 102 gives a phase noise mask/envelope for the clock frequency spectra.

According to AR#63026, the phase noise mask is a preferred method for specifying jitter of the UltraScale GTH/GTY reference clock. 

The websites listed below have calculators that help you convert the phase noise mask into traditional time-measurements of jitter.

https://www.silabs.com/jittercalculator/phase-noise-jitter-calculator.aspx 

https://abracon.com/phaseNoiseCalculator.php

https://www.maximintegrated.com/en/design/technical-documents/app-notes/3/3359.html

The phase noise mask/envelope is well understood by manufacturers of quality clock oscillators.  So, when buying a clock oscillator for your project, give them a phase noise mask specification rather than a jitter(time) specification.  

Finally, if you are buffering the clock before sending it to the FPGA, then include the "added jitter" specification of the buffer in your total budget for GTH clock jitter.

Mark

 

View solution in original post

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Registered: ‎07-23-2019

Re: Zynq ultrascale+ GTH jitter spec?

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The sharpest, clearest answer ever. Thanks.

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Registered: ‎07-23-2019

Re: Zynq ultrascale+ GTH jitter spec?

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There is something I can't square though, in note 2 below table 102 in DS925:

"adjust the phase noise mask values by 20 log (N/312.5)"

So for 100 MHz I get about -10 dB, does that mean I have to add -10 dB to the table figures and make them lower for a lower frequency? That will translate into a lower frequency clock requiring a tighter jitter, is that right?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: Zynq ultrascale+ GTH jitter spec?

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Hi @archangel-lightworks ,

yes, that is correct. To reach the same line rate with a lower reference clock you need a higher multiplication factor for the used PLL. This factor will similarly apply for the noise on the clock. So, to have the same conditions on the serial line, you need a more stringent mask for reference clock with lower frequency.

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Registered: ‎07-23-2019

Re: Zynq ultrascale+ GTH jitter spec?

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Makes sense that way. Therefore it looks reasonable to prefer higher frequencies, like 200-250 MHz instead of 100.

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