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vparashar
Contributor
Contributor
964 Views
Registered: ‎05-22-2018

decoupling capacitors for gty banks

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Dear all,

I want to connect two GTY banks (on two different FPGAs) back to back as shown in below diagram:Capture.PNG

UG 578 on page 337 recommends that 100nF decoupling capacitor should be used for MGTYTX/RX signals. But on eval boards like ZCU111 and ZCU102, Xilinx has not used such capacitors although decaps are used for ref clock  signals only. 

How should I proceed while board design? Thanks

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alesea
Explorer
Explorer
935 Views
Registered: ‎05-08-2018

Do what they say, not what they do,

 

Xilinx verifies their PDN design by using CAD tools followed by bench testing.  The recommendations are designed to work in almost all PCB designs.  Is it over-kill?  Usually, yes.  But, unless you verify it by running the CAD tools on your PCB you should follow their rules.

 

 

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alesea
Explorer
Explorer
936 Views
Registered: ‎05-08-2018

Do what they say, not what they do,

 

Xilinx verifies their PDN design by using CAD tools followed by bench testing.  The recommendations are designed to work in almost all PCB designs.  Is it over-kill?  Usually, yes.  But, unless you verify it by running the CAD tools on your PCB you should follow their rules.

 

 

View solution in original post