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Explorer
Explorer
471 Views
Registered: ‎10-12-2018

gt dbg: key "unit" not known in dictionary

Hi,

I tried to use debug logic insertion based on xapp1295. I get the following error during running insert_gt_dbg analyze mydesign.dcp:

INFO: [Project 1-604] Checkpoint was created with Vivado v2017.4 (64-bit) build 2086221
open_checkpoint: Time (s): cpu = 00:01:18 ; elapsed = 00:00:56 . Memory (MB): peak = 2503.977 ; gain = 1791.227
Step 1 - checking design for GT and BUFG instances and prepare insert_gt_dbg.do
checking clock network ... report_clock_networks: Time (s): cpu = 00:00:51 ; elapsed = 00:00:36 . Memory (MB): peak = 3695.785 ; gain = 1191.809
done
search for GT instances ... key "unit" not known in dictionary

What should I do?


First I use automaticly generated dcp, which leads me to this issue. Now I use manually exported checkpoint. I have no errors and no critical warning in the messages window. Only one simple irrelevant warning printed.

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Xilinx Employee
Xilinx Employee
456 Views
Registered: ‎10-19-2011

Hi @betontalpfa ,

yes, to use the script you need a DCP of the full design that is running on the board. You only get all information into the DCP if you write it out with 'write_checkpoint' from an open synthesised design. Then the analyse step can find the necessary clocking information.

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Explorer
Explorer
448 Views
Registered: ‎10-12-2018

Hi @eschidl 

Sorry I wasn't clear.

I got the error ( "unit" not known in dictionary) with the manually exported checkpoint.

What should I do?

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Xilinx Employee
Xilinx Employee
434 Views
Registered: ‎10-19-2011

Hi @betontalpfa ,

seems you clock network is not fully defined for timing. Please check the generated file insert_gt_dbg.clk_nw. It captures the output of the report_clock_networks command.

You should see clock definitions like this:

Clock rxoutclk_out[3]_1 (312.5MHz)(endpoints: 0 clock, 1 nonclock)

You should have the frequencies given here.

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