gty test

[kongcuiqing]

The input of gty is RXP=1 and RXN=0, and it is observed that the parallel output end of RX is f during simulation, which is the same as the ideal.Online testing, the same conditions, but RX's parallel output is garbled.That's why.

xcku11p

thank you

[behnam_2705new]

what data do you capture from RX?

As you know these pins are differential because of some electrical issues such as denoising, by the way, that is correct to ground N part of the signal to N and connect your signal to the other pin.

do you have  a noisy signal?

[kongcuiqing]

RX's parallel output is garbled, and it is not a fixed value.

I did two experiments

One: in the code, I make the gty core RXP=1 and RXN=0, so the RX input is irrelevant, which means there is no external influence.The only difference between the simulation and the upper panel test is that the simulation power supply is ideal and the upper panel test power supply is given from the board.But will it have such a serious impact?

Second: when I connect the external RX terminal and TX terminal with a cable, I want to collect the data spontaneously. When the program loads successfully, it will also have irregular data on the parallel RX terminal (at this time, TX terminal has not sent number).

To sum up: now it seems that no matter what, as long as the parallel output of RX terminal is measured on the upper board, there will be data, but I don't know where the data comes from, and it doesn't match the simulation, which is really incredible.

[behnam_2705new]

was your cdr locked?

was your reset done signal activated?

could you see power good signal high?

[kongcuiqing]

yes, these signals are valid

[behnam_2705new]

cdr of clock wants a transition to be locked,

Are you sure about cdr locked signal?

[kongcuiqing]

Yes, I'm sure. Just now , I  put GTY's example design on the hardware and found that "rx_data_good_in" is always low, which means that the RX side is receiving the wrong number.I only added two clocks and one reset, is there any requirement for the two clocks of GTY?

[behnam_2705new]

do you use example design without changing?

rx_good is a signal that was connected to the reset module(example_init_inst), reset module duty is reset gt as long as capture the correct data. in the example design prbs32 is the correct data. 

in example design, sm_link signal shows the link status set it always be 1.

be note that after your test you should have your checker to check your data.

you should connect this signal to one and comment module which generates this signal.

[kongcuiqing]

in the example design, if the signal "rx_data_good_in" =1, that means the RX receive the correct data, right? Now, I just want to let the example design to run in the board, so I did not modefy the example. 

[behnam_2705new]

yes, the design check intern data by prbs checker, your data is not PRBS then its obvious that rx_good is always being low.

[kongcuiqing]

yeah, it's where the problem, this signal is low. Now, I am trying to check my ip core. thank you

[behnam_2705new]

:)))

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[behnam_2705new]

post another question please,

someone has good experience in GT transceivers and can help you.

by asking the question in this post you will lose other's help.

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[roym · Accepted solution]

You can use the IBERT to test the function as it has the internal loopback available.  If it gives you an open eye you are in business.  You can also bring the loopback port out of the example design and use it to set up near end pma loopback.  Static signals aren't usually helpful as you need to have a signal for the clock data recovery circuit to lock to.  You also normally have ac coupling capacitors on RXP and RXN that would not allow the DC to get through.