UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Voyager
Voyager
311 Views
Registered: ‎06-26-2015

serde latency

could someone help me understand this table on serde latency

https://www.xilinx.com/support/answers/64309.html    the number are in clk cycles base on ref clk speed. eg 156Mhz etc.  ??

0 Kudos
4 Replies
Xilinx Employee
Xilinx Employee
296 Views
Registered: ‎12-10-2009

Re: serde latency

The numbers are in UI, which is the bit period of the SERDES link.  For example a 10Gb/s link the UI is 100 ps.

Voyager
Voyager
280 Views
Registered: ‎06-26-2015

Re: serde latency

so when it mention 16 then its 16*100ps when lane is 10Gb/s?
0 Kudos
Scholar drjohnsmith
Scholar
266 Views
Registered: ‎07-09-2009

Re: serde latency

yep
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
248 Views
Registered: ‎01-08-2012

Re: serde latency

You need to be careful about the maths though.  The OP is using a "156MHz" clock (presuambly 156.25MHz), making it likely that "10G"  refers to 10G Ethernet which actually runs at 10.3125Gb/s on the line, meaning a UI is 96.97ps rather than 100ps.

0 Kudos