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Visitor brybounbr
Visitor
285 Views
Registered: ‎07-03-2018

transceiver 8b108 recovered clock

Using 8b108 encoded data, at the RX side is the recovered clock the original data rate clock or is it 8b108 encoded line rate clock? 

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3 Replies
Voyager
Voyager
264 Views
Registered: ‎02-01-2013

Re: transceiver 8b108 recovered clock

I assume you're talking about the data rate at the User Interface of some IP that connects to a serial interface that utilizes 8b10b encoding.

The data rate you see is the effective data rate for the interface, not the line rate

For example, a XAUI (for 10-gigbit Ethernet) interface consists of 4, 3.125-Gbps lines, all working in concert, that combine to provide a 12.5 Gbps line rate. The effective data rate, however, is 80% of that--or 10 Gbps.

-Joe G.

 

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Voyager
Voyager
261 Views
Registered: ‎02-01-2013

Re: transceiver 8b108 recovered clock

Dang. You're talking about the clock...
The clock will be commensurate with the effective data rate.
Continuing my XAUI example, since the data at the user interface is 10 Gbps, it could be presented as 64 bits at 156.25 MHz.
Visitor brybounbr
Visitor
233 Views
Registered: ‎07-03-2018

Re: transceiver 8b108 recovered clock

Thanks for you quick response. I've used a 10G SERDES with 64/66 encoding in past that on the RX side its output was 64 bits with 161.13 MHz and we had to multiply the 161.13 x 64/66 to get back to our data rate clock of 156.25MHz. The line interface has to be operating at 161.13Mhz at TX and RX side to process the 66 bits in same time it would take process 64 at 156.25MHz.

So it appears Xilinx is doing the clock extraction and clock rate conversion inside to deliver user data rate clock in the end.

 

 

 

 

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