01-09-2019 08:11 AM
Using 8b108 encoded data, at the RX side is the recovered clock the original data rate clock or is it 8b108 encoded line rate clock?
01-09-2019 10:08 AM
I assume you're talking about the data rate at the User Interface of some IP that connects to a serial interface that utilizes 8b10b encoding.
The data rate you see is the effective data rate for the interface, not the line rate.
For example, a XAUI (for 10-gigbit Ethernet) interface consists of 4, 3.125-Gbps lines, all working in concert, that combine to provide a 12.5 Gbps line rate. The effective data rate, however, is 80% of that--or 10 Gbps.
01-09-2019 10:13 AM
01-09-2019 12:49 PM
Thanks for you quick response. I've used a 10G SERDES with 64/66 encoding in past that on the RX side its output was 64 bits with 161.13 MHz and we had to multiply the 161.13 x 64/66 to get back to our data rate clock of 156.25MHz. The line interface has to be operating at 161.13Mhz at TX and RX side to process the 66 bits in same time it would take process 64 at 156.25MHz.
So it appears Xilinx is doing the clock extraction and clock rate conversion inside to deliver user data rate clock in the end.