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Observer
Observer
948 Views
Registered: ‎09-03-2018

ultrascale transceiver throughput problem

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Hi all,

I use ultrascale transceiver generate a 2.5Ghz serdes . If the throughput isn't 100% ,will it be a problem?

For example, if throughput is 1.25Ghz, it will be half of data signal and idle signal combined in phy signal (rxp or rxn signal). If throughput is 2.5Ghz then will be 100% data signal in phy signal.

And now I find out if throughput is above 1.5Ghz, there is no data loss. But if throughput is 500M or 100M , it will be a lot of data loss(88% and 92%). Is there could be a sample problem or clock isn't lock?

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Observer
Observer
814 Views
Registered: ‎09-03-2018

If it possible that the problem is I use QPLL but not CPLL drive the transceiver?

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Moderator
Moderator
906 Views
Registered: ‎07-30-2007

Usually if you are running at 2.5 Gbps you would be using 8b/10B encoding. This would reduce your maximum throughput by 20%. If you are not using an encoding then you would likely run into problems with DC balance on input ac coupling capacitor which would cause data errors. If you are using the 8B10B encoding then you should be able to send any combination of idle characters and data. You should probably be using LPM equalization. Is this the case?




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Observer
Observer
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Registered: ‎09-03-2018

I am using 8B10B, and I tried 1G serdes. It won't be a problem for 1G serdes(throughput 1G, 500M, 100M, 10M, 1M)

On the other hand, I changed 2.5G serdes's reference clock from 156.25M to 200M, find out if  reference clock is 200M, packet will drop when throughput is 2499M, and then will be worse if throughput going down(1500M loss 1%.500M loss 88% 100M loss 92% ).

When reference clock is 156.25M, only throughput is less then 1500M will have packet loss(1000M 7% 500M 88% 100M 92%).

So it will be the reference clock problem?

p.s. 1G serdes reference clock 156.25M

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Xilinx Employee
Xilinx Employee
881 Views
Registered: ‎08-07-2007

hi @wuperry0125

 

any 8b10b decode error indicated?

 

RXNOTINTABLE

RXDISPERR

 

Thanks,

Boris

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Observer
Observer
876 Views
Registered: ‎09-03-2018

I only use ultrascale transceiver serdes and with my design. and it seem to be RX have something wrong.

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Observer
Observer
872 Views
Registered: ‎09-03-2018

p.s.

This problem only exist in FPGA

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Observer
Observer
815 Views
Registered: ‎09-03-2018

If it possible that the problem is I use QPLL but not CPLL drive the transceiver?

View solution in original post

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