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Visitor acyuzuguler
Visitor
6,009 Views
Registered: ‎07-07-2014

A question about FPGA's power characteristics

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Hi,

 

Theoretically, power consumption of a semiconductor device is expected to be proportional to the square of the clock frequency. However, FPGA chips has a linear power vs frequency characteristics. I wonder what might be the reason behind this? Does anyone have an explanation for why power consumption of FPGA chips increases linearly with clock frequency?

 

Best,

A. Caner Yüzügüler 

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Scholar dwisehart
Scholar
7,479 Views
Registered: ‎06-23-2013

Re: A question about FPGA's power characteristics

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Xilinx Employee
Xilinx Employee
5,986 Views
Registered: ‎07-31-2012

Re: A question about FPGA's power characteristics

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Hi,

 

Where did you read about the linearity of the power with clock frequency. 

 

The power consumption in an FPGA depends on many factors as the logic inside the FPGA is not fixed. 

 

Based on the different component utilizations and the clock used for that, the power consumption increases. You can check the XPE spreadsheet and input values based on your expected device utilization to check the pwoer consumed - http://www.xilinx.com/products/design_tools/logic_design/xpe.htm

Thanks,
Anirudh

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Visitor acyuzuguler
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5,984 Views
Registered: ‎07-07-2014

Re: A question about FPGA's power characteristics

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I have tested it personally. I only changed clock frequency of my design (output of PLL) without modifying the design while resource usage, toggle rates etc. remain unchanged and measured the current supplied from Vccint. When I plot 'power vs frequency' graph over 5 MHz and 500MHz , I observed that it is exactly linear. Besides, XPE also indicates a linear increase on power when the clock frequency is increased.

 

My question is, a usual silicon transistor's power consumption is directly proportional to the square of the clock frequency. But for a Xilinx FPGA chip, it is linearly increasing with clock frequency. Is it possible Xilinx uses a different technology with such a power characteristics?  

 

Best,

A. Caner Yüzügüler

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Xilinx Employee
Xilinx Employee
5,970 Views
Registered: ‎01-03-2008

Re: A question about FPGA's power characteristics

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> Theoretically, power consumption of a semiconductor device is expected to be proportional to the square

> of the clock frequency.

 

You need to go back and check your textbooks, but this wrong.   Dynamic power is approximately = C*V^2*F

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Scholar dwisehart
Scholar
7,480 Views
Registered: ‎06-23-2013

Re: A question about FPGA's power characteristics

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Instructor
Instructor
5,847 Views
Registered: ‎08-14-2007

Re: A question about FPGA's power characteristics

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Just to beat this dead horse one more time, the power is linear with frequency because power is energy per unit time, and the energy to switch a capacitance on or off once is fixed for a given voltage.  Twice the frequency will switch the capacitor twice as many times in a second, or twice the energy per second, hence twice (not 4 times) the power.

-- Gabor