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Participant heiyux
Participant
10,294 Views
Registered: ‎02-19-2009

Can I use TWO SPI Flash for two V6 FPGA configration with a single jtag chain

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Hi there,

     I'm about to use two pieces of XC6VST315T. Since the configration bit file is huge and I'm short of IO pins, I want to use TWO SPI Flash like N25Q128-1.8V to config the FPGAs. 

     I can find the guide of two FPGA with ONE SPI Flash using Mutiboot MSC File, which set the first FPGA connected to SPI Flash in Master SPI mode(Mode pin 001) and set the second FPGA in Slave Serial mode(Mode pin 111).

     But in my design, one SPI Flash with the max supported density 128Mb is not enough. So I want to use two SPI Flash, one for each FPGA. And I have trouble finding the guides about this situation. I want two FPGAs to connect as a single jtag chain, and therefor the second FPGA should work in  Slave Serial mode(Mode pin 111). I don't kown if the second FPGA in Slave Serial mode can use Indirect in-system programming to program the SPI Flash.

     I draw a simple block diagram to show my intention as following. I show the main signal connection and haven't drew some necessary resister and the voltage connection. I want to kown if this circuit can work out and if not, how to modify or what other method can I use?

 

Thanks very much!

Day.

SPI_chain.png
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1 Solution

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Instructor
Instructor
11,956 Views
Registered: ‎08-14-2007

Re: Can I use TWO SPI Flash for two V6 FPGA configration with a single jtag chain

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If you need 128 Mb per device, then you can connect a SPI flash to each V6 and set

each V6 in Master SPI mode.  Don't connect the CCLK pins together (each chip will

boot independently - this is also faster).  You may connect the DONE pins together if

you want the devices to start up synchronously.  However because they won't share

the same startup clock unless you define a "user" clock for startup, you may need to

find other ways to synchronize the start-up.

 

The JTAG chain should be OK as you show it, however check the user guide for recommendations

on pull-up resistors (all signals except TDO), and termination on the TCK line.

 

Any device on the JTAG chain can use indirect SPI programming (as long as the flash device is

supported by Impact).

 

-- Gabor

-- Gabor
7 Replies
Instructor
Instructor
11,957 Views
Registered: ‎08-14-2007

Re: Can I use TWO SPI Flash for two V6 FPGA configration with a single jtag chain

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If you need 128 Mb per device, then you can connect a SPI flash to each V6 and set

each V6 in Master SPI mode.  Don't connect the CCLK pins together (each chip will

boot independently - this is also faster).  You may connect the DONE pins together if

you want the devices to start up synchronously.  However because they won't share

the same startup clock unless you define a "user" clock for startup, you may need to

find other ways to synchronize the start-up.

 

The JTAG chain should be OK as you show it, however check the user guide for recommendations

on pull-up resistors (all signals except TDO), and termination on the TCK line.

 

Any device on the JTAG chain can use indirect SPI programming (as long as the flash device is

supported by Impact).

 

-- Gabor

-- Gabor
Teacher eteam00
Teacher
10,274 Views
Registered: ‎07-21-2009

Re: Can I use TWO SPI Flash for two V6 FPGA configration with a single jtag chain

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Gabor's comments are spot on.

 

If you connect the two FPGAs as in your original diagram, I suspect that Impact (via JTAG) will be unable to program the "slave" SPI flash memory.  Both FPGAs should be strapped for Master (SPI) Serial configuration, with separate CCLKs.

 

For development and debugging purposes, you may wish to control the two PROG_B pins individually.  You should also separate the INIT_B pins.  The benefit of ANDing the INIT_B pins together is (I believe) specifically for daisy-chain configuration topology, and will work against you for concurrent Master configuration.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Participant heiyux
Participant
10,260 Views
Registered: ‎02-19-2009

Re: Can I use TWO SPI Flash for two V6 FPGA configration with a single jtag chain

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Hi Gabor,

 

Thanks very much! That's exact what I want to kown.

 

I wil connect the DONE pins together and let them boot independently, since my design doesn't need them to boot exactly synchronous. And your advice about necessary resistors will be taken.

 

Thanks!

Day.

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Participant heiyux
Participant
10,259 Views
Registered: ‎02-19-2009

Re: Can I use TWO SPI Flash for two V6 FPGA configration with a single jtag chain

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Hi Bob,

 

Thanks very much! You complete Gabor's adivce.

 

Your adivce is useful. If I tie the two PROG_B pins together, then the two FPGA must config together everytime. 

 

I understand your adivce of INIT_B pins in this way:  Since the two PROG_B pins is separated, if I reconfig one FPGA by pull down its PROG_B pin, then it's INIT_B pin will go low after and will affect the other FPGA. But if I tie the two PROG_B pins together and just make them reconfig together everytime, then the ANDing INIT_B pins will be OK since holding INIT_B pin can delay the configration. Is my understanding correct?

 

Thanks!

Day.

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Teacher eteam00
Teacher
10,251 Views
Registered: ‎07-21-2009

Re: Can I use TWO SPI Flash for two V6 FPGA configration with a single jtag chain

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I understand your adivce of INIT_B pins in this way:  Since the two PROG_B pins is separated, if I reconfig one FPGA by pull down its PROG_B pin, then it's INIT_B pin will go low after and will affect the other FPGA.

 

If FPGA #2 is already configured, transitions on its INIT_B input (caused by FPGA #1, for example) should have no effect.  Unless you are enabling SEU analysis (if you don't know what SEU analysis is, you aren't using it).

 

But if I tie the two PROG_B pins together and just make them reconfig together everytime, then the ANDing INIT_B pins will be OK since holding INIT_B pin can delay the configration.

 

This is true only when INIT_B is held low before configuration begins -- before its initial transition HIGH.  From UG380:

There are two ways to delay configuration for Spartan-6 devices:

-- Hold the INIT_B pin Low during initialization. When INIT_B has gone High, configuration cannot be delayed by subsequently pulling INIT_B Low.

 

The INIT_B pin has another purpose: an indicator of a configuration error.  If both FPGAs are tied to a single INIT_B net, it's more difficult to figure out which FPGA experienced the configuration error when and if it occurs.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Participant heiyux
Participant
10,235 Views
Registered: ‎02-19-2009

Re: Can I use TWO SPI Flash for two V6 FPGA configration with a single jtag chain

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Hi Bob,

 

     Thanks for your explanation! It's very detailed. I think I should separated them for the debuging.

 

Thanks again!

Day.

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Participant heiyux
Participant
10,232 Views
Registered: ‎02-19-2009

Re: Can I use TWO SPI Flash for two V6 FPGA configration with a single jtag chain

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I shoud say, both Gabor's and Bob's answer are very helpful and accurate. But I can only choose one for the Solution. Thanks!
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