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Voyager
Voyager
11,777 Views
Registered: ‎07-28-2008

2014.4.1 stuck at Executing elaborate step ...

I have relative small design, about 3% of Kintex7-325t.

 

While implementation from scratch takes about 1.5hrs. Simulation seems to stuck at "Executing elaborate step..."

 

elaborate.log shows:

 

 

Vivado Simulator 2014.4
Copyright 1986-1999, 2001-2014 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2014.4/bin/unwrapped/win64.o/xelab.exe -wto 1cd677141e17408cacabe67d79cb63de --debug typical --relax -L fifo_generator_v12_0 -L xil_defaultlib -L blk_mem_gen_v8_2 -L xbip_utils_v3_0 -L xbip_pipe_v3_0 -L xbip_bram18k_v3_0 -L mult_gen_v12_0 -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_Top_behav xil_defaultlib.tb_Top xil_defaultlib.glbl -log elaborate.log 
Multi-threading is on. Using 6 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis

I have no idea, what's going on. Tool setup seems to fine, since I can simulate dummy testing design.

 

Please advise how to troubleshoot this.

 

Thanks,

8 Replies
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Xilinx Employee
Xilinx Employee
11,763 Views
Registered: ‎10-24-2013

Re: 2014.4.1 stuck at Executing elaborate step ...

Hi,
Try disabling multi threading also check with 2015.1
Thanks,Vijay
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Moderator
Moderator
11,586 Views
Registered: ‎04-17-2011

Re: 2014.4.1 stuck at Executing elaborate step ...

Can you post a testcase here?
Also, how much time is it waiting in that stage?
Regards,
Debraj
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Voyager
Voyager
11,517 Views
Registered: ‎07-28-2008

Re: 2014.4.1 stuck at Executing elaborate step ...

Thanks a lot for looking into my issue.

 

I am quite certain, my design source confused tool somehow; My project is messy uncompleted code base with a lot of critical warnings. But it implemented with some timing failure.

 

I was expecting just to get behavior simulation. I also reduced testbench to just one process of $display and clock generation.

 

I've tried 2015.1 same stuck. I was expecting to be able to pull a bit more info or trouble shooting log. Any verbose log?

 

But on the other side, simulation kicks off quickly in ModelSim.

 

Will keep investigating and share my finding here.

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Moderator
Moderator
11,414 Views
Registered: ‎04-17-2011

Re: 2014.4.1 stuck at Executing elaborate step ...

In XSIM turn on the verbose setting for elaboration:

verbose.JPG

Regards,
Debraj
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Observer
Observer
5,003 Views
Registered: ‎07-24-2017

Re: 2014.4.1 stuck at Executing elaborate step ...

Debrajr,

    I came across this thread when investigating what I thought was an excessive elab time.  I have what I think is a simple design and I am getting unusually long elab times.  I turned on verbose in the sim elab, and I get more messages, but there are no messages coming out when processing is "stalled".  I see 2 cores running during this time so elab is definitely running.  The project eventually simulates OK.  I have a much larger project that also has a very long elab time.  What were we supposed to see when you suggested turning on verbose messages?

 

Windows 7/64 viv 2015.2, vhdl

 

Thanks,

Ed

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Contributor
Contributor
4,422 Views
Registered: ‎03-29-2016

Re: 2014.4.1 stuck at Executing elaborate step ...

Bumping thread.

I am seeing the same issue. All the verbose messages show me are the generics I'm passing into each file from the top level test-bench. Elaborating for days.

CentOS7 Vivado 2015.4 Design Ed.
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Moderator
Moderator
4,400 Views
Registered: ‎06-24-2015

Re: 2014.4.1 stuck at Executing elaborate step ...

@gutel

 

Can you give it a try with latest version of Vivado i.e. 2017.3?

Thanks,
Nupur
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Observer
Observer
4,141 Views
Registered: ‎08-14-2012

Re: 2014.4.1 stuck at Executing elaborate step ...

I don't know if it is related, but in case it is useful in the investigation of this issue, I am seeing exceedingly long elaboration times with Cadence ncelab when I use both the UNISIM_VER library and our own tech library for a piece of gate-level verilog in the design.

 

If I leave out one small file from the design (about 100 lines gate level verilog), elaboration takes less than 4 minutes, equally if I leave out the Xilinx PCIe IP and include the gate level it is about the same.

 

With the full design present, it takes over an hour to elaborate (but does eventually simulate correctly).

 

With the full design when I run ncelab on its own with "-libverbose" option, I see ncelab is stuck churning on looking for the PCIE_2_1 core, which it eventually finds in UNISIMS_VER.