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Visitor cjm99999
Visitor
10,620 Views
Registered: ‎12-10-2014

2015.1 IP testbench work directory

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What am I missing?  I create a new project with nothing in it.  I add a single IP from the IP catalog that has an included testbench, such as FFT, FIR or Complex Multiply.  I let it do OOC and it completes with no errors.  I set the simulation testbench as top. I run behavioral simulation.  Get error such as...

 

Running: C:/Xilinx/Vivado/2015.1/bin/unwrapped/win64.o/xelab.exe -wto ebdb16602c2c41858d28249abd1df006 --debug typical --relax --mt 2 -L xbip_utils_v3_0 -L axi_utils_v2_0 -L xbip_pipe_v3_0 -L xbip_bram18k_v3_0 -L mult_gen_v12_0 -L cmpy_v6_0 -L xil_defaultlib -L secureip --snapshot tb_cmpy_0_behav xil_defaultlib.tb_cmpy_0 -log elaborate.log


Using 2 slave threads.

 

ERROR: [XSIM 43-3225] Cannot find design unit xil_defaultlib.tb_cmpy_0 in library work located at xsim.dir/work.

 

There is no "work" directory anywhere.  All the files I can find have there library set to xil_defaultlib.  I have read all the simulation user guides and tutorials, all the using IP user guides and tutorials.  Searched the web and these forums.  Found poeple with similar issues but everything that was mentioned, I tried and didn't work.

 

Vivado 2015.1 Webpack, Windows 7 Pro 64bit.

 

Chris

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Xilinx Employee
Xilinx Employee
16,133 Views
Registered: ‎07-16-2008

Re: 2015.1 IP testbench work directory

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I can reproduce the failure by setting the IP testbench as top. The problem is due to the tb_cmpy_0.vhd not included in the .prj file that I mentioned earlier.

 

This is a Vivado flow issue. To work around it, disable OOC setting and re-generate IP product. This allows correct .prj file to be generated and hence no elaboration error.

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Scholar pratham
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Registered: ‎06-05-2013

Re: 2015.1 IP testbench work directory

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@cjm99999 Check this and try

 

http://www.xilinx.com/support/answers/58937.html

-Pratham

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Moderator
Moderator
10,614 Views
Registered: ‎01-16-2013

Re: 2015.1 IP testbench work directory

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Hello @cjm99999,

 

The error occurs because the testbench file is not successfully compiled. 

This is usually due to a missing file in the project file (.prj) generated by Vivado.

You can check the project file in the <project_name>.sim/sim_1/synth/func/ directory. 

If the file is missing in the automatically generated .prj file, you can try the following methods:

 

  1. Create a custom project file and run simulation from the command line.
  2. Check the hierarchy update mode in the Sources window.
    Ensure it is set to "Automatic Update and Compile Order".
  3. Check the testbench file properties and ensure the Used In property includes Simulation.
    Try removing and re-adding the source to see if it makes any difference.

Thanks,

Syed

 

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Did you check our new quick reference timing closure guide (UG1292)?
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Visitor cjm99999
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10,608 Views
Registered: ‎12-10-2014

Re: 2015.1 IP testbench work directory

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Ok.  I had seen this but it talked about post Synthesis simulation so I didn't follow through.

 

Unfortunately I am not skilled with Tcl so am not quite sure what ti use for the  <file_name>.v/vhd parameter in my case.  I'll keep working on it but any help would be be appreciated.

 

Chris

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Visitor cjm99999
Visitor
10,599 Views
Registered: ‎12-10-2014

Re: 2015.1 IP testbench work directory

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Well I might be totally confused but I don't have any directories under <project_name>.sim/sim_1.  No /synth or anything else.  I am trying to do behavioral simulation and I assume that these testbenches will have everything I need to create the IP as the top module and have the vectors to drive it.  Maybe I'm wrong?

 

I did have "Automatic Update and Compile Order" set already. 

 

I might be missing something basic.  Is there any tutorials on simulating IP from the catalog without using the downloaded example projects?

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Moderator
Moderator
10,589 Views
Registered: ‎01-16-2013

Re: 2015.1 IP testbench work directory

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HI @cjm99999,

 

Here is the Vivado Simulation Tutorial:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug937-vivado-design-suite-simulation-tutorial.pdf

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Visitor cjm99999
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Registered: ‎12-10-2014

Re: 2015.1 IP testbench work directory

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Like I said, a tutorial the does NOT start from the downloaded example projects!

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Moderator
Moderator
10,545 Views
Registered: ‎04-17-2011

Re: 2015.1 IP testbench work directory

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I went through this thread and here is my opinion:

1. When you create the IP from IP catalog, it is as you told added to the Sources window under sim_1 (Simulation set) and the output products are generated in OOC mode (it creates a synthesized checkpoint file (.dcp) for you).


2. You then can do a right-click on the IP and Open IP Example Design (most of the IP's will have this option) and it opens a new Vivado GUI for you with an example testbench under sim_1 and it instantiates the IP. You can run behavioral simulation and check the waveform.


3. If you have your own testbench, you have to open the .vho/.veo file generated by the IP (while running Generate Output products) and copy the instantiation template to your testbench. Add clock, reset and other inputs signals to the IP and run Behavioral Simulation.


4. Usually for behavioral simulation the directory is project_sim/sim_1/behav/


5. I have attached a small example project were in I have a testbench which instantiates an IP and you can run simulation (though I dont have clock etc, you can see that there is no error, once the waveform window opens you can force clock and some inputs, if you want)

Regards,
Debraj
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Visitor cjm99999
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10,529 Views
Registered: ‎12-10-2014

Re: 2015.1 IP testbench work directory

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Thanks for the reply.  But....

 

1. I have no problems when I write my "own" test bench which instantiates the IP from the IP catalog.  That works fine for me. 

 

2. I have no problems when I can do the right click and open example the example design.  That works fine also.  But not all the IP have this option. For example the Complex Multiply.  It has a test bench when you create it but there is no example design.

 

My issue is how do I run behavioral simulation with that test bench that comes with the complex multiply???  Whatever I do I get an error like...

 

ERROR: [XSIM 43-3225] Cannot find design unit xil_defaultlib.tb_cmpy_0 in library work located at xsim.dir/work.

 

It's not just the Complex Multiply either.  I've tried FFT, FIR Filter and a couple others.

 

pratham suggested this link http://www.xilinx.com/support/answers/58937.html

but I'm not sure what files to use that command on.  Haven't had any success yet.

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Xilinx Employee
Xilinx Employee
10,522 Views
Registered: ‎07-16-2008

Re: 2015.1 IP testbench work directory

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@cjm99999 wrote:

Well I might be totally confused but I don't have any directories under <project_name>.sim/sim_1.  No /synth or anything else.  I am trying to do behavioral simulation and I assume that these testbenches will have everything I need to create the IP as the top module and have the vectors to drive it.  Maybe I'm wrong?

 

I did have "Automatic Update and Compile Order" set already. 

 

I might be missing something basic.  Is there any tutorials on simulating IP from the catalog without using the downloaded example projects?


Did you launch the simulation by clicking Run Simulation > Run Behavioral Simulation in the flow navigator of Vivado IDE?

If yes, you should be able to see <project_name>.sim/sim_1/behav directory. Here the sim_1 corresponds to the simset in your project. That is, if you launch simulation on simset sim_2, you need to look for <project_name>.sim/sim_2/behav.

 

You might have a look at section "Simulating IP" in UG895 (v2015.1), Pg55. But there's no step-by-step instructions like in tutorial.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug896-vivado-ip.pdf

 

Once you are able to locate the simulation directory, I would like to see the .prj file so as to confirm the testbench is correctly compiled to xil_defaultlib.

 

If it's possible, please attach the project archive for further investigation.

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Visitor cjm99999
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Registered: ‎12-10-2014

Re: 2015.1 IP testbench work directory

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Here are the steps I use to see the error.  I've tried many variations with no success.  I can't upload a project do to my companies security policies.

 

1. Launch vivado 2015.1 webpack.
2. Click on create new project.
3. Project type RTL, do not specify sources at this time is checked.
4. Target language is verilog, simulation is mixed.(have tried other settings)
5. Click next.
6. Accept the default part, xc7k70tfbv676-1.
7. Finish creating project_1.
8. Double click Complex Multiplier in IP catalog.
9. Click OK on custumizations to accept all default settings.
10. On Generate Output Products window, Select Out Of Context per IP and click Generate.
11. Allow generation to finish.
12. Under Flow Navigator/Simulation, click Run Simulation and then Run Behavioral Simulation.
13. Get Window asking for top module and click cancel.
14. Under Sources/Simulation Sources/sim_1, expand cmpy_0 and right click on tb_cmpy_0 and set as top module.
15. Under Flow Navigator/Simulation, click Run Simulation and then Run Behavioral Simulation.
16. Critical Message window pops up and go Tcl Console or log and see the error I describe.

 

 

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Xilinx Employee
Xilinx Employee
16,134 Views
Registered: ‎07-16-2008

Re: 2015.1 IP testbench work directory

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I can reproduce the failure by setting the IP testbench as top. The problem is due to the tb_cmpy_0.vhd not included in the .prj file that I mentioned earlier.

 

This is a Vivado flow issue. To work around it, disable OOC setting and re-generate IP product. This allows correct .prj file to be generated and hence no elaboration error.

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