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Voyager
Voyager
3,629 Views
Registered: ‎04-04-2014

2017.2 Vivado Sim error message reporting

I am guessing this isn't confined to 2017.2 and has been the case for a few release but...what is going on with the error message reporting in simulation? By this I mean:

 

1 The Dynamic Syntax Checking doesn't work for sim files (This is warnings and notes, I do see the red squiggle for errors).

2 When a simple error is encountered the message window doesn't report the actual error, it just tells me to check the xvhdl.log file

 

I am sure no 2 was not the case for my last version, 2014.2. If I forget a semicolon do I really have to open my file browser and drill down 4 folders into my project and open a log file in a separate text editor just to be told that? Or am I missing a setting somewhere that will actually put the relevant message in the message window and give me a hyperlink to take me to the offending line?

 

And can we sort out no1? O, again, have I missed a setting?

 

Thanks

 

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7 Replies
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Moderator
Moderator
3,607 Views
Registered: ‎04-24-2013

Re: 2017.2 Vivado Sim error message reporting

 

Hi @mistercoffee,

 

I ran a small test in 2017.2 and I can see the red squiggle when there is a syntax error, the tools also shows the line number of the syntax error in the tcl console although it can be hard to spot it

 

ERROR: [VRFC 10-1412] syntax error near reg [H:/forums/project_2/project_2.srcs/sim_1/imports/Sources/bft_tb.v:32]

 

It may be easier to spot in the Messages tab, see below

 

You can also run the check_syntax command in the tcl console at any stage to update the messages.

 

Untitled.png

 

Let me know if this helps.

Best Regards
Aidan

 

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Voyager
Voyager
3,601 Views
Registered: ‎04-04-2014

Re: 2017.2 Vivado Sim error message reporting

Ok, I cannot repeat this. See my screenshot here. I have created an intentional syntax error by removing the semicolon from the end of a line (currently above the one highlighted in the text editor). FYI, this is the top level for the simulation sources, the testbench file itself. I also saved the file first, before you ask.

 

2017_error_msg.png

 

As you can see there is no red squiggle highlighting the error in the sources tab. There is also no relevant error in the messages tab.

If I put a similar error into one of the non-simulation sources (the design top level for instance) I again see no red squiggle in the sources tab but the line beneath does highlight orange with a Warning. See here:

 

2017_error_msg2.png

 

If it helps I am running windows 10 and VHDL sources. Have I missed a setting?

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Moderator
Moderator
3,556 Views
Registered: ‎04-24-2013

Re: 2017.2 Vivado Sim error message reporting

Hi @mistercoffee

 

I reran the test on a vhd simulation source as suggested and removed the semi-colon from line 46.

 

The syntax error doesn't show here but you get the error highlighted when the undefined signal is used.

You can manually check for syntax errors at any stage using the check_syntax tcl command. (in blue)

 

Syntax.png

The errors show up in the tcl console and the messages tab when you launch the run, simulation, synthesis etc . (in green)

This means that you don't have to dig down the 4 directory levels to open the log file to see what the error was.

 

There is a usability trade off with how and how often the tools run the syntax checking.

 

If you have a text editor that you prefer (or does better syntax checking) then you can change the default editor that Vivado uses under Tools, Settings, General, Text Editor.

 

Let me know if this helps

Best Regards
Aidan

 


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Voyager
Voyager
3,546 Views
Registered: ‎04-04-2014

Re: 2017.2 Vivado Sim error message reporting

Ok, apologies in advance because this is basically going to be a rant I think.

 

Firstly, when I launch a simulation I do not always get an error that indicates the syntax error. I very often (not every time but a lot) get an error message that just says to check the xvhdl.log file. This was my original complaint really, that a very common and easy to make mistake takes a lot of trouble to find the cause. 

 

So, your post suggests that the there is a difference in expected behaviour depending on whether the source file is vhdl or verilog? Again, odd and not particularly useful. 

 

Also, behaviour is different depending on whether it is a simulation file or not, again not very helpful.

 

I do understand compromises are necessary to balance the usability and performance of the tool. It just seems especially odd seen as though the later versions of the tool are, by having the dynamic syntax checking feature included, claiming to improve productivity in this respect. My experience here clearly goes against that. What is also baffling is that this was not the case in earlier tool versions. In my last 2014.2 I would always see the offending file indicated in the sources tab and if I attempted to run a sim with the error in there the error message would be helpful and allow me to find the problem quickly. Suggesting I could try an alternative text editor when your own text editor previously behaved satisfactorily, with regards to error reporting, is just silly.

 

Sorry for the rant, but you can see why people get frustrated. 

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Moderator
Moderator
3,538 Views
Registered: ‎04-24-2013

Re: 2017.2 Vivado Sim error message reporting

Hi @mistercoffee

 

No problem at all, it's good to get the feedback.

 

Just a quick clarification on two of the points:

 

There is no difference in the expected behaviour between verilog and vhdl source files, if I suggested this it was unintentional.

 

Likewise there is no difference in the behaviour of the parser between synthesis sources and simulation sources. If you open the same source file in both the Sim and Synth views and create an error then it should be highlighted identically. If you have an example where this doesn't happen then let me know and I can have it investigated.

 

I compared the results of creating an error in 2017.2 and 2014.2 and there is a difference in the behaviour.

In 2014.2 the file name is highlighted and in 2017.2 the error is highlighted within the file.

 

Syntax1.png
I will bring this to the development team to see if the file name can also be included.

 

Best Regards
Aidan

 

 

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Voyager
Voyager
3,429 Views
Registered: ‎04-04-2014

Re: 2017.2 Vivado Sim error message reporting

Apologies for the late reply, I have been out of office. Also, while I was out my PC has been rebuild with a new windows 10 install, and hence a new Vivado 2017.2 install, as I had issues before. There is no difference in my observed behaviour now my PC has been fixed.

So...

 


@amaccre wrote:

 

 

 

Likewise there is no difference in the behaviour of the parser between synthesis sources and simulation sources. If you open the same source file in both the Sim and Synth views and create an error then it should be highlighted identically. If you have an example where this doesn't happen then let me know and I can have it investigated.

 

  


Firstly, I don't see the file highlighted (with red squiggle) in the sources tab, like you have shown in your screenshot. I took my top level design source and deleted the semicolon from the end of a signal declaration like you did. The sources tab remains unchanged. Having the syntax error highlighted there was useful when I used to use 2014.2. When I do this the line following the syntax error is highlighted orange. 

 

Secondly if I take my top level test bench (which calls my top level design source) there is no error indication whatsoever. The source file is not highlighted with a red squiggle in the sources tab and the line following the error is not highlighted orange. The only indication I get is if I try to run a sim and then I get an error during compilation that says to check my xvhdl.log file.

 

Clearly, what I am seeing is different to what you observe. It would appear there is a problem with my install or project or something else. What do you suggest I do now? 

 

Thanks

 

 

 

 

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Voyager
Voyager
3,291 Views
Registered: ‎04-04-2014

Re: 2017.2 Vivado Sim error message reporting

I don't suppose I could get an answer or some progress on this?

 

Just to give an example of how much time I waste because of this problem, here is one I just experienced.

 

- I mistakenly added a syntax error.

- This caused an error to flash up saying that my top level module was no longer valid.

- My hierarchy was automatically dismantled and all source files included under the heading "non-module files"

- I opened up all the recently edited source files I had been working on and none gave any indication at all that there was a syntax error anywhere in the file.

- There were no helpful messages in the message window. The only error was a srcscanner error no 139

 

After approx half an hour of searching for the error, which included rebuilding the project from scratch with my build script because I had started to think the project was corrupt, I found the error.

 

The error was in a source file 2 levels down in the hierarchy. I had forgotten to add "end component;" to the end of a component declaration. Again, even when I knew where it was I could see it had not been indicated in any way.

 

This is not acceptable guys. I would like an answer either way. 

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