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Voyager
Voyager
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Registered: ‎05-14-2017

2019.2 - ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Hello,

I need to simulate a custom Verilog design but when I run the whole process I get stuck with this error:

 

launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/tmp/axicountertest/axicountertest.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/opt/Xilinx/Vivado/2019.2/data/xsim/xsim.ini' copied to run dir:'/tmp/axicountertest/axicountertest.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/tmp/axicountertest/axicountertest.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj testbench_vlog.prj
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/tmp/axicountertest/axicountertest.sim/sim_1/behav/xsim'
xelab -wto 887b39cb1c90456c9f969602940a14eb --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2019.2
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab -wto 887b39cb1c90456c9f969602940a14eb --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "/tmp/axicountertest/axicountertest.srcs/sources_1/ip/AxiStreamCounter_0/AxiStreamCounter.v" Line 2. Module AxiStreamCounter_default doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.AxiStreamCounter_default
Compiling module xil_defaultlib.AxiStreamCounter_0
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'/tmp/axicountertest/axicountertest.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/tmp/axicountertest/axicountertest.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

 

It seems that there's a problem with xil_defaultlib.glbl, but I don't know nothing about it.

What is the best way to debug this ?

Thanks.

s.

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Voyager
Voyager
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Registered: ‎05-14-2017

Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Problem solved. I was missing libncurses5

sudo apt-get install libncurses5

What I have done to debug it is to execute, from shell, the same Vivado command with -v 2 option from xsim directory (in my case is project_1/project_1.sim/sim_1/behav/xsim).

First export RDI_DATADIR to Vivado's data directory:

export RDI_DATADIR=/opt/Xilinx/Vivado/2019.2/data/

then, from xsim dir:

/opt/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab -wto 78786a6820c048c394541a08f3e7aa04 --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log -v 2

which finally shows:

/opt/Xilinx/Vivado/2019.2/data/./../tps/llvm/3.1/lnx64.o/bin/clang: error while loading shared libraries: libncurses.so.5: cannot open shared object file: No such file or directory
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting... 

This was not shown in Vivado Tcl console !

I strongly recommend to increase verbosity.

Regards.

s.

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12 Replies
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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Hi @simozz 

Add the verbose switch (i.e., -v 2) to xelab which will provide more information about the problem.
Check page no. 146 in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug900-vivado-logic-simulation.pdf 

Thanks,
Vinay

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Voyager
Voyager
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Registered: ‎05-14-2017

Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Hello @vuppala ,

The xelab_log.txt attachment is the log of the manual execution of the command:

xelab -v 2 -wto 887b39cb1c90456c9f969602940a14eb --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log

from Vivado's Tcl console. This is the command I see that Vivado executes when I launch behavioral simulation.

At the last line the log reports:

ERROR: [XSIM 43-3225] Cannot find design unit xil_defaultlib.testbench in library work located at xsim.dir/work.
child process exited abnormally

As an extra info, my simulation model is called testbench (testbench.v).

Thanks.

s.

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Voyager
Voyager
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Registered: ‎05-14-2017

Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Hello @vuppala,

Can you extract any useful information to find out a solution for this issue ?

Thanks,

s.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Hi @simozz

Are you setting testbench.v as top-module in simulation sources i.e., sim_1 in the project?

Thanks,
Vinay
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Voyager
Voyager
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Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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@vuppala

yes, but the error persists.

s.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Hi,

Can you share your testcase here?

Thanks,
Vinay
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Voyager
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Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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@vuppala, this is:

`timescale 1ns/1ps 

module testbench;

    reg aresetn;
    reg m_axis_aclk;
    
    reg t_ready;
    
    AxiStreamCounter_0 asc(
        .M_AXIS_TREADY(t_ready),
        .aresetn(aresetn),
        .m_axis_aclk(m_axis_aclk)
    ); 
    
    initial begin
        t_ready <= 1;
        aresetn <= 1;
        m_axis_aclk <= 0;
        
        forever m_axis_aclk <= ~m_axis_aclk;
        
        #1 aresetn <= 0;
        #1 aresetn <= 1;
        
        #100 $finish;
    end
   
endmodule

Actually I don't see any particular error in it.

AxiStreamCounter_0 is a custom Master AXI4-Stream counter that I am already using in another design.

Regards,

s.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Hi @simozz 

The below line in your testbench is missing #time to generate the proper clock.

forever m_axis_aclk <= ~m_axis_aclk;

you have to specify #time to toggle the clock. If your clock period is 10ns, modify the above line as below:

forever #5 m_axis_aclk <= ~m_axis_aclk;

Thanks,
Vinay

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Voyager
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Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Hello @vuppala ,

Thank you for your suggestion, but it doesn't solve the problem, neither Vivado warns about it. :(

The same error persists. There isn't any way to increase the debug and see what is going on ?

s.

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Voyager
Voyager
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Registered: ‎05-14-2017

Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Hello @vuppala ,

Can you confirm that is not required to have a design source with the IP to simulate ?

This is my sources window:

Screenshot_2020-02-12_11-29-33.png

I remember I have simulated custom IPs with older Vivado versions (for example 2017.2) but it's quiet strange I cannot simulate it now and I cannot see any other claims about it.

s.

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Voyager
Voyager
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Registered: ‎05-14-2017

Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Unuseful content delete by @simozz .

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Voyager
Voyager
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Re: ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c

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Problem solved. I was missing libncurses5

sudo apt-get install libncurses5

What I have done to debug it is to execute, from shell, the same Vivado command with -v 2 option from xsim directory (in my case is project_1/project_1.sim/sim_1/behav/xsim).

First export RDI_DATADIR to Vivado's data directory:

export RDI_DATADIR=/opt/Xilinx/Vivado/2019.2/data/

then, from xsim dir:

/opt/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab -wto 78786a6820c048c394541a08f3e7aa04 --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log -v 2

which finally shows:

/opt/Xilinx/Vivado/2019.2/data/./../tps/llvm/3.1/lnx64.o/bin/clang: error while loading shared libraries: libncurses.so.5: cannot open shared object file: No such file or directory
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/testbench_behav/obj/xsim_1.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting... 

This was not shown in Vivado Tcl console !

I strongly recommend to increase verbosity.

Regards.

s.

View solution in original post