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Visitor alawi
Visitor
6,563 Views
Registered: ‎04-07-2014

7Segment display with a clock

Hi, I wrote a VHDL thats supposed to run 4 displays simultnasly with each display showing different output.

the first display shows the input from SW(15 downto 12) 

the second from SW(11 downto 8)

etc.

 

The code works without errors, but only one diplay is working. It seems to me that the clock is not functiong as it should. can anyone help me with the syntax of the clock to enable four displays?

 

Here is my code:

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 02/28/2014 03:55:05 PM
-- Design Name: 
-- Module Name: project_5 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity project_5 is
--generic (N: integer := 4);
    port(
          SW : in STD_LOGIC_VECTOR(15 downto 0);
          SSEG_CA : out STD_LOGIC_VECTOR (6 downto 0);
          SSEG_AN : inout STD_LOGIC_VECTOR (7 downto 0);
          LED : inout STD_LOGIC_VECTOR(7 downto 0);
          clk : in STD_LOGIC;
          clr : in STD_LOGIC;
          dp: out STD_LOGIC
                    );
                    
 end project_5;
          
architecture Behavioral of project_5 is

signal digit: STD_LOGIC_VECTOR ( 3 downto 0);
signal s:STD_LOGIC_VECTOR ( 1 downto 0);
signal aen: STD_LOGIC_VECTOR ( 3 downto 0);
signal clkdiv: STD_LOGIC_VECTOR ( 19 downto 0);


begin

s <= clkdiv(19 downto 18);
aen <= "1111";
dp <= '1';

clock: process(clk, clr)
begin
    if clr = '1' then
         clkdiv <= (others => '0');
    elsif clk'event and clk = '1' then
         clkdiv <= clkdiv +1;
    end if;
 end process;
 
 -- representaion on 7seg display
segrep: process(digit)
begin


        case digit is
            when "0000" => SSEG_CA <= "1000000"; --0
            when "0001" => SSEG_CA <= "1111001"; --1
            when "0010" => SSEG_CA <= "0100100";  --2
            when "0011" => SSEG_CA <= "0110000"; --3
            when "0100" => SSEG_CA <= "0011001"; --4
            when "0101" => SSEG_CA <= "0010010"; --5
            when "0110" => SSEG_CA <= "0000010";  --6 
            when "0111" => SSEG_CA <= "1111000";  --7
            when "1000" => SSEG_CA <= "0000000"; --8
            when "1001" => SSEG_CA <= "0010000"; --9
            when "1010" => SSEG_CA <= "0001000"; --A
            when "1011" => SSEG_CA <= "0000011"; --b
            when "1100" => SSEG_CA <= "1000110"; --C
            when "1101" => SSEG_CA <= "0100001"; --d  
            when "1110" => SSEG_CA <= "0000110"; --E
            when others => SSEG_CA <= "0001110";  --F
     end case;
    
end process;

-- Select display
selan: process(s, aen)
begin
    SSEG_AN <= "11111111";
    if aen (conv_integer(s)) = '1' then
        SSEG_AN(conv_integer(s)) <= '0';
    end if;
end process;

pnew: process(s, SW)
begin 
    case s is
      
        when "00" => digit <= SW(15 downto 12);
         when "01" => digit <= SW(11 downto 8);
         when "10" => digit  <= LED(3 downto 0);
        when others => digit <= LED(7 downto 4);
     end case;
     
end process;   


 
p3: process(SW, LED)
begin

-- -- -- -- --
-- need to fix this 
-- -- -- -- --

case SW(1 downto 0) is
when "00" =>
      LED(3 downto 0) <= SW(15 downto 12) + SW(11 downto 8);
when "01" =>
      LED(3 downto 0) <= SW(15 downto 12) - SW(11 downto 8);
when "10" =>
      LED(3 downto 0) <= SW(15 downto 12) AND SW(11 downto 8);
when "11" =>
      LED(3 downto 0) <= SW(15 downto 12) OR SW(11 downto 8);
when others =>
      LED(3 downto 0) <= "0000";      
end case;

-- -- -- -- --
-- need to fix this 
-- -- -- -- --
case SW(3 downto 2) is

when "00" =>
    LED(7 downto 4) <= LED(3 downto 0);
when "01" =>
--    no LED(7 downto 4) <= LED(6 downto 0) & LED(7);
 LED(7 downto 4) <= LED(7) & LED(6 downto 4) ;
when "10" =>
 --   no  LED(7 downto 0) <= LED(0) & LED(7 downto 1);
  LED(7 downto 4) <= LED(7 downto 5) & LED(4);
  
when "11" =>
 LED(7 downto 4) <= NOT(LED (7 downto 4));
when others =>
 LED(7 downto 4) <= "0000";      
end case;



     
end process;

end Behavioral;


 

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2 Replies
Xilinx Employee
Xilinx Employee
6,550 Views
Registered: ‎07-01-2008

Re: 7Segment display with a clock

This forum is for Implementation Tool issues and so isn't an ideal forum for your design implementation question. You may still get a good answer here, but I recommend that you try the General Technical Discussion forum instead.

Moderator
Moderator
6,491 Views
Registered: ‎04-17-2011

Re: 7Segment display with a clock

Suggestion: Process p3 can be updated as
p3: process(clk, SW, LED)
if (clk'event and clk='1') then
....
end case;
end if;

Do you have a testbench for this code so that you can simulate it? Would you mind sharing it with us.
Regards,
Debraj
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