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mawagner2
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Registered: ‎06-28-2010

AXI VIP: 'IF' is not declared under prefix 'inst'

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Hi, I have several Vivado projects containing the AXI VIP. None of them works anymore.

For example, a small project containing only the AXI VIP as master and a AXI BRAM as slave gives following error:

ERROR: [VRFC 10-2991] 'IF' is not declared under prefix 'inst' [C:/Users/th51wg/Desktop/test_vip/test_vip.srcs/sim_1/new/testbench_vip.sv:56]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

The source hierarchy is shown as this:

mawagner2_0-1631618257019.png

There is no axi_vip_v1_1_8_top found in the xil_defaultlib?

Also, when starting the simulator, no XilinxAXIVIP is found.

This is my testbench:

// Test bench

import block_design_axi_vip_0_0_pkg::*;
import axi_vip_pkg::*;

//Declare agent
block_design_axi_vip_0_0_mst_t mst_agent;

module testbench_vip(
);

reg clk;
reg reset_n;

block_design_wrapper dut (.clk(clk), .resetn(reset_n));

// Simple Reset Generator and test
initial begin
reset_n = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge clk);
reset_n = 1'b1;
@(posedge clk);
end

// Simple Clock Generator
initial clk = 1'b0;
always #10 clk = !clk;

// VIP agent
initial begin
mst_agent = new("my VIP agent",testbench_vip.dut.block_design_i.axi_vip_0.inst.IF);
end


endmodule

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mawagner2
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Registered: ‎06-28-2010

A reinstallation of Vivado solved the problem.

View solution in original post

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graces
Moderator
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279 Views
Registered: ‎07-16-2008

Please check out some similar previous posts and see if the solutions help.

https://forums.xilinx.com/t5/Alveo-Accelerator-Cards/Alveo-Vivado-design-flow-axi-vip-fails-in-behavior-simulation/m-p/1116229/highlight/false#M1677

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/AXI-VIP-IF-is-not-declared-under-prefix-inst/td-p/1199359

 

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mawagner2
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Registered: ‎06-28-2010

This didn't help. It seem that almost none of the necessary files are include during axi vip instantiation.

Only axi_vip_v1_1_vl_rfs.sv exists. Files like e.g. axi_vip_1_pkg.sv are not there. What could be the reason for this?

 

 

 

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mawagner2
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Registered: ‎06-28-2010

Even the VIP example design has this problem:

ERROR: [VRFC 10-2991] 'IF' is not declared under prefix 'inst' [../../../../imports/axi_vip_0_mst_stimulus.svh:81]
ERROR: [VRFC 10-2991] 'IF' is not declared under prefix 'inst' [../../../../imports/axi_vip_0_passthrough_mem_stimulus.svh:60]
ERROR: [VRFC 10-2991] 'set_slave_mode' is not declared under prefix 'inst' [../../../../imports/axi_vip_0_passthrough_mem_stimulus.svh:73]
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [../../../../imports/axi_vip_0_passthrough_mem_stimulus.svh:154]
ERROR: [VRFC 10-2649] an enum variable may only be assigned the same enum typed variable or one of its values [../../../../imports/axi_vip_0_passthrough_mem_stimulus.svh:164]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

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amaccre
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Registered: ‎04-24-2013

Hi @mawagner2 

Can you check that your project settings are set to Verilog and not VHDL.

What version of the tools are you trying to run this in?

Best Regards
Aidan

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mawagner2
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Registered: ‎06-28-2010

The language was set to mixed. Setting it to Verilog did not improve the situation.

I am using Vivado 2020.2 with the integrated simulator

 

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amaccre
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Registered: ‎04-24-2013

HI @mawagner2 ,

You need to check the Target Language in the General tab of the settings as well as the Simulator language settings

amaccre_0-1631798019094.png

I created a test project using the AXI VIP example design and ran it in Vivado 2020.2 (see attached)

To do this I created a blank project, added a Block Design and then added the AXI VIP to this.

I right clicked on the IP in the Block Design and choose open example design.

When this opened it ran simulation without any errors.

amaccre_1-1631798313478.png

 

Can you try and replicate these steps to see if this works for you?

It is important the language is set to Verilog in both places.

Best Regards
Aidan

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mawagner2
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Registered: ‎06-28-2010

No, this didn't work either. Even the project you attached gave the following errors when trying to simulate:

ERROR: [VRFC 10-2991] 'IF' is not declared under prefix 'inst' [../../../../axi_vip_0_ex.srcs/sim_adv_mst_active__pt_passive__slv_comb/imports/imports/axi_vip_0_mst_stimulus.svh:82]
ERROR: [VRFC 10-2991] 'IF' is not declared under prefix 'inst' [../../../../axi_vip_0_ex.srcs/sim_adv_mst_active__pt_passive__slv_comb/imports/imports/axi_vip_0_passthrough_mem_stimulus.svh:60]
ERROR: [VRFC 10-2991] 'set_slave_mode' is not declared under prefix 'inst' [../../../../axi_vip_0_ex.srcs/sim_adv_mst_active__pt_passive__slv_comb/imports/imports/axi_vip_0_passthrough_mem_stimulus.svh:73]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

Maybe there is something wrong with my Vivado installation?

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amaccre
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Registered: ‎04-24-2013

Hi @mawagner2 ,

You could definitely try a reinstall, this has helped other people in the forums. If you do, make sure that you are using a supported version of the OS, these are listed here for 2020.2:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug973-vivado-release-notes-install-license.pdf#_OPENTOPIC_TOC_PROCESSING_d114e2223

If using Windows 10, be aware that the latest 20H2 update is not supported as it was not released when the 2020.2 version of the tools were and so has not been tested.

Best Regards
Aidan

 

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mawagner2
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Registered: ‎06-28-2010

A reinstallation of Vivado solved the problem.

View solution in original post

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