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370 Views
Registered: ‎02-25-2019

AXI VIP simulation error

vivado printed information:

5825000 : testbench.DUT.hp_axi3_vip_slv.inst.genblk1.PC.REP  : BIT(     37) : ERROR : AXI_ERRM_ARADDR_BOUNDARY: Aburst must not cross a 4kbyte boundary.Spec: section A3.4.1

13235000 : testbench.DUT.gp_axi3_vip_slv.inst.genblk1.PC.REP  : BIT(     37) : ERROR : AXI_ERRM_ARADDR_BOUNDARY: Aburst must not cross a 4kbyte boundary.Spec: section A3.4.1

FATAL_ERROR:Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will ternimate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Time: 3917585 ns Iteration: 2 Process: /axi_vip_pkg/axi_slv_wr_driver(C_AXI_PROTOCOL=1,C_AXI_WID_WIDTH=1,C_AXI_RID_WIDTH=1,C_AXI_HAS_QOS=0):File:/wrk/2017.4/nightly/2017_12_15_2086221/prep/rdi/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv

HDL Line:/wrk/2017.4/nightly/2017_12_15_2086221/prep/rdi/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv :1474

WARNING:[Simulator 45-29] Cannot open source file /wrk/2017.4/nightly/2017_12_15_2086221/prep/rdi/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv:file does not exist.

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6 Replies
Moderator
Moderator
318 Views
Registered: ‎11-09-2015

Re: AXI VIP simulation error

Hi @greenbirdflybiubiu 

Crossing a 4K boundary is forbidden by the AXI spec. You might want to make sure you are solving this first on your master then it can solve the exceptional condition.

Crossing a 4K boundary mean that you have a burst starting before a boundary and ending after.

The boundaries are

xxxxxFFF to xxxxx000


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
296 Views
Registered: ‎02-25-2019

回复: AXI VIP simulation error

Hi @florentw
Thank you so much for your reply!

I hanve solved the 4KB boundary problem ,but the fatal error still exists.


FATAL_ERROR:Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will ternimate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Time: 890755 ns Iteration: 2 Process: /axi_vip_pkg/axi_slv_wr_driver(C_AXI_PROTOCOL=1,C_AXI_WDATA_WIDTH=64,C_AXI_RDATA_WIDTH=64,C_AXI_WID_WIDTH=1,C_AXI_RID_WIDTH=1,C_AXI_HAS_QOS=0)::get_rd_reactive

File:/wrk/2017.4/nightly/2017_12_15_2086221/prep/rdi/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv

HDL Line:/wrk/2017.4/nightly/2017_12_15_2086221/prep/rdi/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv :14299
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Moderator
Moderator
293 Views
Registered: ‎11-09-2015

回复: AXI VIP simulation error

HI @greenbirdflybiubiu 

Can you share a test case?

What vivado version are you using?

What OS are you working on ?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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280 Views
Registered: ‎02-25-2019

回复: AXI VIP simulation error

Hi @florentw
I am sorry, I could not share the case due to permission issues.
Vivado 2017.4
OS: win10
I used to AXI_VIP in one case, one for GP port (data width:32bit), another for HP port(data width:64bit).
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Moderator
Moderator
267 Views
Registered: ‎11-09-2015

回复: AXI VIP simulation error

HI @greenbirdflybiubiu 

Could you try with a newer version of vivado?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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257 Views
Registered: ‎02-25-2019

回复: AXI VIP simulation error

OK,I will try it.
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