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Explorer
Explorer
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Registered: ‎03-26-2010

AXI and Zynq BFM in VHDL environment

Hi all,

 

I'm making extensive use of the BFM in a Verilog/SystemVerilog design and verification framework for Vivado and things are working out. However, my company is committed to using OS-VVM and VHDL in testbenches as much as possible, I'm the only Verilog user...

 

What has been done to make the BFM function in a VHDL testbench? If there's nothing off the shelf, what's a good way to get started creating VHDL wrappers for BFM-related Verilog functions like bfm_inst.write_data() etc.? I'm using Vivado 2014.x.

 

Thanks!

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