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toussaic
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Registered: ‎08-24-2012

AXI4-Stream Interconnect, Simulation Wrapper, Error 104

Hello,

 

I try to simulate a design with two AXI4-Stream Interconnect IP, with different configuration (1 way to 8 ways; and 8 ways to 1 way).

In other posts, I found that we have to comment the following lines in the "***_sim.vhd" file:

 

LIBRARY axis_interconnect_v1_1;
USE axis_interconnect_v1_1.axis_interconnect_v1_1_axis_interconnect_16x16_top;

Or change it to this :

 

LIBRARY work;
USE work.axis_interconnect_v1_1_axis_interconnect_16x16_top;

And because all the generics are defined as integer, I changed the values in the instanciation (for example) :

 

C_M00_AXIS_CONNECTIVITY => X"FFFF",
with :
C_M00_AXIS_CONNECTIVITY => 16#FFFF#,

It works when I have only one instanciation of the IP. But I need two of them.

 

Because there is no library declared for each instanciation, each component of the IP is redeclared. For example, the warning apparead in the console :

 

Analyzing Verilog file "***/ipcore_dir/AXI_Interconnect_Read/hdl/verilog/axis_interconnect_v1_1_axisc_sync_clock_converter.v" into library work

... (some others lines)

WARNING:HDLCompiler:687 - "***/ipcore_dir/AXI_Interconnect_Write/hdl/verilog/axis_interconnect_v1_1_axisc_sync_clock_converter.v" Line 62: Illegal redeclaration of module <axis_interconnect_v1_1_axisc_sync_clock_converter>.

 

Then I have these kind of error :

 

ERROR:HDLCompiler:918 - "***/ipcore_dir/AXI_Interconnect_Write/hdl/verilog/axis_interconnect_v1_1_axis_interconnect_16x16_top.v" Line 634: Size mismatch in mixed language port association, verilog port M08_AXIS_TDATA

 

I tried many things but none worked :

I tried to create new libraries and to add the xco files to those libraries but we can't change the library of a xco file.

I tried to add all of the vhdl / v files needed in new libraries but it calls some other libraries and It makes a very huge  number of files in the projet manager. Moreover I have some errors.

 

Maybe there is a much easier way but I can't find it. Any suggestions ?

 

Here the links to the other posts :

http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/Library-error-AXI4-IPcores/m-p/314321

 

http://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-streaming-interconnect-core-simulation-in-own-project/m-p/293929/highlight/true#M8798

 

Of course, I use the last version of ISE and the last version of  the IP.

 

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