04-21-2020 01:48 AM
In my new project I use a CI pipleline for automated testing and it makes things much easier. Sigasi already integrated VUnit into Sigasi Studio.
XSIM should support at least all the VHDL features needed for VUnit.
Atm this is not possible with Vivado/Xsim and makes it useless to me.
It is very poor that I have to rely on third party tools to work with the design flow that is state of the art
04-27-2020 12:52 AM - edited 04-27-2020 12:56 AM
04-27-2020 12:55 AM - edited 04-27-2020 12:57 AM
@richardhead The main problem is GHDL just support vhdl, in my case I need to use Vunit with Verilog. I´ve been cheking the possibility to simulate with other open source simulators but it is not possible, only with Mentor...
04-27-2020 01:05 AM
What cores are you trying to use?
Ram can easily be infered from VHDL, so a generic FIFO can also be easily written in VHDL.
if anything else, then yes, its a pain, and mixed language is the only option.
02-04-2021 05:29 AM - edited 02-04-2021 05:29 AM
Support for VUnit with Vivado would be a big plus to me as well. Unfortunately, at the moment I cannot see any sign that this will happen any time soon.
At a minimum, it would be nice if Vivado could analyze testbenches, which include the VUnit context clause, without throwing an error.