03-19-2017 07:15 AM
When will this be supported?
ERROR: [XSIM 43-4187] File "...vhdl" Line 26 : The "Vhdl 2008 Record with Unconstrained Element" is not supported yet for simulation.
03-19-2017 09:55 AM
For VHDL-2008, only a limited set of feauture is supported in Vivado Simulator. From your ERROR message, it seems that you have something like
entity top is
architecture arch of top is
The moment you use 'fixed_pkg', it means that you are using package instantiation as fixed_pkg is nothing but instance of generic package like
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
So those features, which are not supported, you should see ERROR message ID 43-4187. If your intention is not to use the fixed_pkg, please modify your test case.
can you check if the following AR helps
refer chapter-5 in the following link
also check appendix e from the following link
03-19-2017 12:03 PM
No, I'm intentionally using an unconstrained member of a record, and wondering when Xilinx will support it (and all of 2008).
01-17-2019 02:13 AM - edited 01-17-2019 02:15 AM
Interesting - because they work fine in synthesis, as of 2017.4. (I use ActiveHDL for simulation - I have code that I doubt will ever be supported in vivado)
Can you post the code you're trying to use?
01-17-2019 02:54 AM
05-16-2019 10:25 AM
Absolutely! It is extremely annoying to have the same feature supported in synthesis and not in simulation!
05-16-2019 10:35 AM