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Observer
Observer
3,806 Views
Registered: ‎11-28-2014

Arrays/Records with unconstrained elements (2008)

When will this be supported?

 

ERROR: [XSIM 43-4187] File "...vhdl" Line 26 : The "Vhdl 2008 Record with Unconstrained Element" is not supported yet for simulation.

 

8 Replies
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Xilinx Employee
Xilinx Employee
3,794 Views
Registered: ‎08-01-2008

Re: Arrays/Records with unconstrained elements (2008)

For VHDL-2008, only a limited set of feauture is supported in Vivado Simulator. From your ERROR message, it seems that you have something like

_________

library ieee;
use ieee.fixed_pkg.all;

entity top is
end;

architecture arch of top is
begin
end;

_______

The moment you use 'fixed_pkg', it means that you are using package instantiation as fixed_pkg is nothing but instance of generic package like

_________

 

library IEEE;

package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
);

_________

So those features, which are not supported, you should see ERROR message ID 43-4187. If your intention is not to use the fixed_pkg, please modify your test case.

 

can you check if the following AR helps

http://www.xilinx.com/support/answers/62005.html

 

refer chapter-5 in the following link

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_3/ug901-vivado-synthesis.pdf

 

also check appendix e  from the following link 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug900-vivado-logic-simulation.pdf

Thanks and Regards
Balkrishan
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Observer
Observer
3,778 Views
Registered: ‎11-28-2014

Re: Arrays/Records with unconstrained elements (2008)

No, I'm intentionally using an unconstrained member of a record, and wondering when Xilinx will support it (and all of 2008).

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Visitor
Visitor
883 Views
Registered: ‎09-30-2018

Re: Arrays/Records with unconstrained elements (2008)

I am still experiencing this exact same problem in Vivado 2018.3! This needs to be fixed...

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Scholar
Scholar
874 Views
Registered: ‎08-01-2012

Re: Arrays/Records with unconstrained elements (2008)

@lsav

Interesting - because they work fine in synthesis, as of 2017.4. (I use ActiveHDL for simulation - I have code that I doubt will ever be supported in vivado)

Can you post the code you're trying to use?

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Visitor
Visitor
871 Views
Registered: ‎09-30-2018

Re: Arrays/Records with unconstrained elements (2008)

@richardhead apologies, i meant this happens in behavoural simulation

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Scholar
Scholar
860 Views
Registered: ‎08-01-2012

Re: Arrays/Records with unconstrained elements (2008)

@lsav

I understand this - but still, would be good to see the code Vivado is choking on. It seems odd there isnt parity between synth and simulation.

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Contributor
Contributor
597 Views
Registered: ‎02-24-2016

Re: Arrays/Records with unconstrained elements (2008)

Absolutely! It is extremely annoying to have the same feature supported in synthesis and not in simulation!

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Teacher
Teacher
592 Views
Registered: ‎07-09-2009

Re: Arrays/Records with unconstrained elements (2008)

Good luck,
based upon what we see, VHDL does not appear to be high on the Xilinx to do list.

Now if you were into a new thing like AI, then you might be in luck
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