[BD 41-237] Bus Interface property FREQ_HZ does not match
I got this error message when I compiled my design with a system ILA connected to a AXI interconnect:
[BD 41-237] Bus Interface property FREQ_HZ does not match between /system_ila_0/SLOT_0_AXI(100000000) and /axi_cpu_interconnect/tier2_xbar_1/M00_AXI(99990005)
The problem is the ILA expect 100MHz and the AXI interconnect of 99.990005MHz, clocked by pl_clk0 from the UltraScale+, I can't change the pl_clk0 frequency to exact 100MHz due to the limited granularity.
Is there anyway to get around that or demote this error into warning?