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Observer jfrenzel
Observer
8,932 Views
Registered: ‎09-30-2008

Behavioral simulation of Distributed Memory - view memory contents

I am using Vivado 2014.4 to perform a behavioral simulation of a design with a distributed memory core (ver. 8.0-rev 7 of the generator). Under ISE 14.4 and Isim (and older dist. mem gen) I could "drill" down through the hierarchy and wave the memory contents, but I haven't been able to do the same under Vivado.

 

Does anyone know how to accomplish this (or if it is possible)?

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4 Replies
Observer jfrenzel
Observer
8,923 Views
Registered: ‎09-30-2008

Re: Behavioral simulation of Distributed Memory - view memory contents

I neglected to mention that my design is in SystemVerilog, so I believe I'm using the simulatior in mixed-HDL mode, since I think the behavioral model of the dist mem is in VHDL. Haven't gotten a chance to try a "pure VHDL" sim yet.

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Xilinx Employee
Xilinx Employee
8,914 Views
Registered: ‎07-31-2012

Re: Behavioral simulation of Distributed Memory - view memory contents

Hi,

 

In 2014.4 most of the IP's are encrypted. Can you cross check if the DRAM core is also encrypted. If it is encrypted you many not be able to add those signals to observe.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Observer jfrenzel
Observer
8,899 Views
Registered: ‎09-30-2008

Re: Behavioral simulation of Distributed Memory - view memory contents

Just to clarify: It is not a DRAM (i.e., dynamic RAM), it is a distributed memory core, generated using the Xilinx Distributed Memory Generator (and build out of LUTS). I would be very surprised if it is encrypted. (but may try and check)

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Observer jfrenzel
Observer
8,837 Views
Registered: ‎09-30-2008

Re: Behavioral simulation of Distributed Memory - view memory contents

I haven't gotten a chance to try behavioral simulation of a distributed memory using VHDL and Vivado, but I'm surprised no one in the community knows the answer. (Why I can't view the memory contents under behavioral sim of a SystemVerilog model.

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