03-04-2015 05:24 PM
I am using Vivado 2014.4 to perform a behavioral simulation of a design with a distributed memory core (ver. 8.0-rev 7 of the generator). Under ISE 14.4 and Isim (and older dist. mem gen) I could "drill" down through the hierarchy and wave the memory contents, but I haven't been able to do the same under Vivado.
Does anyone know how to accomplish this (or if it is possible)?
03-04-2015 07:19 PM
I neglected to mention that my design is in SystemVerilog, so I believe I'm using the simulatior in mixed-HDL mode, since I think the behavioral model of the dist mem is in VHDL. Haven't gotten a chance to try a "pure VHDL" sim yet.
03-04-2015 09:36 PM
In 2014.4 most of the IP's are encrypted. Can you cross check if the DRAM core is also encrypted. If it is encrypted you many not be able to add those signals to observe.
03-05-2015 12:43 PM
Just to clarify: It is not a DRAM (i.e., dynamic RAM), it is a distributed memory core, generated using the Xilinx Distributed Memory Generator (and build out of LUTS). I would be very surprised if it is encrypted. (but may try and check)
03-11-2015 10:48 AM
I haven't gotten a chance to try behavioral simulation of a distributed memory using VHDL and Vivado, but I'm surprised no one in the community knows the answer. (Why I can't view the memory contents under behavioral sim of a SystemVerilog model.