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Visitor raff5184
Visitor
306 Views
Registered: ‎02-21-2019

Bitstream to test a FIFO in Block Design

Hi all,

I have a simple block design including a FIFO generator, a clock wizard and a custom IP block (I'm not using a PS in my design, only Logic).

Can I generate a bitstream that I can feed to the FIFO for SIMULATION, directly in the Block Desgin to test (simulate) my system? Or do I need to write a testbench?

I was able to do this with a Constant IP but I would like to do it with a more than 1 constant value.

 

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Xilinx Employee
Xilinx Employee
291 Views
Registered: ‎02-27-2019

回复: Bitstream to test a FIFO in Block Design

Hi @raff5184 ,

  I think you'd better to follow the Flow Navigator to finish your design . Writing a testbench is a good way.

Capture.PNG

Generate Bitstream is the final step, before it , you have to consider others, not just simulation.

Yang

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Visitor raff5184
Visitor
277 Views
Registered: ‎02-21-2019

回复: Bitstream to test a FIFO in Block Design

thank you @yangc 

what do you mean specifically?

I used other options for input, such as constant values. But how do I test/simulate my system if I don't give the input (bitstream) that it has to work with?

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Xilinx Employee
Xilinx Employee
266 Views
Registered: ‎02-27-2019

回复: Bitstream to test a FIFO in Block Design

Hi @raff5184 ,

  A good way is writing testbench. And you can also use the IP (simulation clock and reset) in block design , that you can not write testbench if your input is connected with Constant.

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Moderator
Moderator
252 Views
Registered: ‎04-24-2013

Re: Bitstream to test a FIFO in Block Design

Hi @raff5184 ,

When you have created your Block Design, right click on it in the sources tab and choose Create Wrapper.

This will create an RTL wrapper that you can use as the target / unit under test for your testbench.

In the Simulation sources add a testbench and set the stimulus to the values you require.

If you are new to writing test benches then have a look at XAPP199 which has advice and examples.

https://www.xilinx.com/support/documentation/application_notes/xapp199.pdf

Best Regards
Aidan

 

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Visitor raff5184
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238 Views
Registered: ‎02-21-2019

Re: Bitstream to test a FIFO in Block Design

@amaccre thank you.

My problem was actually something simpler, probably my question wasn't clear. I am able to create the IP and a testbench, I was wondering if Vivado has an IP block that sends a continous stream of bits, like the Constant IP but with an infinite flow of data.

But your answers are clear thank you

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Moderator
Moderator
229 Views
Registered: ‎04-24-2013

Re: Bitstream to test a FIFO in Block Design

Hi @raff5184 ,

If you are using AXI then have a look at the AXI VIP 

The AXI VIP is for verification and system engineers who want to:
• Monitor transactions between two AXI connections
• Generate AXI transactions
• Check for AXI protocol compliance

https://www.xilinx.com/support/documentation/ip_documentation/axi_vip/v1_1/pg267-axi-vip.pdf

Best Regards
Aidan

 

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