02-07-2018 02:12 PM
I am using Xilinx Zynq VIP in my design simulation environment. I found that AXI_HP0 port doesn’t function correctly. AXI_HP0 has to assert the RVALID signal, But it never got asserted. I also searched the solution on the Xilinx Forums and found that many people has same problem as explained below in the following thread. I have asked the work around in the same thread But nobody from Xilinx replied.
I need to get the work around for this problem in order to make progress on my project. Your urgent help is needed in this regard.
06-26-2018 07:54 AM