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kuldipspx
Observer
Observer
1,713 Views
Registered: ‎08-09-2012

CR 991325 Update Needed

I am using Xilinx Zynq VIP in my design simulation environment. I found that AXI_HP0 port doesn’t function correctly. AXI_HP0 has to assert the RVALID signal, But it never got asserted. I also searched the solution on the Xilinx Forums and found that many people has same problem as explained below in the following thread. I have asked the work around in the same thread But nobody from Xilinx replied.

 I need to get the work around for this problem in order to make progress on my project. Your urgent help is needed in this regard.

 

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Zynq-7000-Verification-IP-S-AXI-HP0-doesn-t-assert-RVALID/m-p/814407/highlight/false#M17190

 

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3 Replies
chrisz
Xilinx Employee
Xilinx Employee
1,667 Views
Registered: ‎05-06-2008

Hello Kuldipspx,

 

This CR is still being investigated by the development team.

 

Thanks,
Chris

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zyanwu
Observer
Observer
1,425 Views
Registered: ‎12-14-2013

Hi @chrisz,

Any updates on this CR?

 

Z

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chrisz
Xilinx Employee
Xilinx Employee
1,415 Views
Registered: ‎05-06-2008

Hello @zyanwu,

 

The notes of the CR state that this issue is resolved in the latest version of Vivado.  I recommend upgrading to Vivado 2018.2.

 

Thanks,

Chris

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