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sebastian_z
Explorer
Explorer
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Registered: ‎04-01-2016

Cadence IES and unisim.vcomponents

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Hi all,

 

I simulate my design with Cadence IES. Now I have a little problem with the vcomponents of UNISIM library. I compile the Xilinx Unisim libraries with a script doing the following:

 

-makelib unisim
-f ${DB_DIR}/design/ip/test_fw/xilinx_libs/xilinx_unisim.f
-endlib

The file xilinx_unisim.f contains the following line:

 

# used unisim primitives for simulation

$XILINX/ids_lite/ISE/verilog/src/unisims/*.v

 

Before I explain my problem in more detail I should tell that the simulation as well as the synthesis is working but I have to change the source file.

I use a BUFGCE instantiation. If I instantiate the module the following way, Vivado can synthesise but simulation is not working.

 

LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.all;

Library UNISIM;
    use UNISIM.vcomponents.all;

entity SPI_Master is
    port (
        -- input clock from PLL
        clk                             : in std_logic;
        -- SPI
        spi_cs                          : out std_logic;
        spi_sck                         : out std_logic;
        spi_mosi                        : out std_logic;
        spi_miso                        : in std_logic
    );
end entity;



architecture Behavioral of SPI_Master is

   // signal declaration    

begin

    
    BUFGCE_inst : BUFGCE
    --generic map (
        --CE_TYPE           => "SYNC",    -- ASYNC, SYNC
        --IS_CE_INVERTED    => '0',       -- Programmable inversion on CE
        --IS_I_INVERTED     => '0'        -- Programmable inversion on I
    --)
    port map (
        O => spi_sck_int,
        CE => spi_sck_en,
        I => clk
    );
    
    

Cadence IES refuses to compile with the following error message:

 

simulation.png

 

If I change to direct instantiation, simulation is working but Xilinx complains:

 

LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.all;

Library UNISIM;
    use UNISIM.vcomponents.all;

entity SPI_Master is
    port (
        -- input clock from PLL
        clk                             : in std_logic;
        -- SPI
        spi_cs                          : out std_logic;
        spi_sck                         : out std_logic;
        spi_mosi                        : out std_logic;
        spi_miso                        : in std_logic
    );
end entity;



architecture Behavioral of SPI_Master is
    
begin

    
    BUFGCE_inst : entity  unisim.BUFGCE
    --generic map (
        --CE_TYPE           => "SYNC",    -- ASYNC, SYNC
        --IS_CE_INVERTED    => '0',       -- Programmable inversion on CE
        --IS_I_INVERTED     => '0'        -- Programmable inversion on I
    --)
    port map (
        O => spi_sck_int,
        CE => spi_sck_en,
        I => clk
    );
    
    

In this case, Cadence has no problem but Vivado tells that there is no such design unit in library UNISIM.

 

I don't really understand what the problem is.

 

I hope anyone can help!

Kind regards

Sebastian

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Accepted Solutions
sebastian_z
Explorer
Explorer
2,645 Views
Registered: ‎04-01-2016

Hi @thakurr

 

thank you very much for your reply.

I solved the issue the following way and post it here, perhaps it is helpful to other users: I added the VHDL file for this components, so my file for the unisim library files (for Cadence IES) contains the following lines:

 

# used unisim primitives for simulation

$XILINX/ids_lite/ISE/verilog/src/unisims/*.v
$XILINX/ids_lite/ISE/vhdl/src/unisims/unisim_VCOMP.vhd

I added the second line and then I don't need the direct instantiation because IES is able to find the package with the component declaration and Vivado is also satisfied. :)

 

Kind regards

Sebastian

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2 Replies
thakurr
Moderator
Moderator
2,136 Views
Registered: ‎09-15-2016

Hi @sebastian_z

 

>>Cadence IES refuses to compile with the following error message:

Please check the below AR for this error in IES simulator:

https://www.xilinx.com/support/answers/40023.html

 

>>If I change to direct instantiation, simulation is working but Xilinx complains.In this case, Cadence has no problem but Vivado tells that there is no such design unit in library UNISIM.

There have been few limitations with direct instantiation method in Vivado so far. For example direct instantiation is not supported when using submodule OOC flow. Change request has been filed on this.

Also Vivado tool search for work library by default hence complains of the missing design unit in the library UNISIM.

 

Regards

Rohit

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Regards
Rohit
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sebastian_z
Explorer
Explorer
2,646 Views
Registered: ‎04-01-2016

Hi @thakurr

 

thank you very much for your reply.

I solved the issue the following way and post it here, perhaps it is helpful to other users: I added the VHDL file for this components, so my file for the unisim library files (for Cadence IES) contains the following lines:

 

# used unisim primitives for simulation

$XILINX/ids_lite/ISE/verilog/src/unisims/*.v
$XILINX/ids_lite/ISE/vhdl/src/unisims/unisim_VCOMP.vhd

I added the second line and then I don't need the direct instantiation because IES is able to find the package with the component declaration and Vivado is also satisfied. :)

 

Kind regards

Sebastian

View solution in original post