11-03-2018 12:11 PM
I'm using Vivado 2018.2 and the recommended Modelsim PE 10.6c (mixed VHDL and Verilog supported). When I compile the simulation libraries, they seem to be empty. For example, the unisim library looks like this:
I've attached the log file from the library compile for the unisim folder. One thing that I'm suspicious of is that there are a lot of references to "nt64". The Modelsim PE simulator is a 32-bit simulator, and I am using the -32 switch (and you can see it in the log file). I do get the warning at the top of the file:
** Warning: (vcom-159) Mode option -32 is not supported in this context and will be ignored.
Which is something new, but it does seem to use the -32 switch in the vcom command to compile the files. Any insight would be appreciated.
11-04-2018 03:55 PM
Can you please share the vivado.log and the compile_simlib.log files to check. As from the log you have shared i see that the unisim libraries have been compiled succeessfully without any error messages.
Also, can you please elaborate more on why they seem to be empty?
11-05-2018 07:59 AM
I am glad to know that you were able to resolve the issue. Can you please close this thread by marking your reply with resolution as accepted solution.