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Observer
Observer
1,259 Views
Registered: ‎07-22-2013

Can't Compile Xilinx Libraries on Modelsim PE

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I'm using Vivado 2018.2 and the recommended Modelsim PE 10.6c (mixed VHDL and Verilog supported). When I compile the simulation libraries, they seem to be empty.  For example, the unisim library looks like this:

 

unisim.jpg

I've attached the log file from the library compile for the unisim folder.  One thing that I'm suspicious of is that there are a lot of references to "nt64".  The Modelsim PE simulator is a 32-bit simulator, and I am using the -32 switch (and you can see it in the log file).  I do get the warning at the top of the file:

 

** Warning: (vcom-159) Mode option -32 is not supported in this context and will be ignored.

 

Which is something new, but it does seem to use the -32 switch in the vcom command to compile the files.  Any insight would be appreciated.

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Observer
Observer
1,210 Views
Registered: ‎07-22-2013

Thanks for the reply. This turned out to be a simple path error on my part.  Or, too much work and not enough sleep!

View solution in original post

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Moderator
Moderator
1,225 Views
Registered: ‎09-15-2016

Hi @djmpap,

 

Can you please share the vivado.log and the compile_simlib.log files to check. As from the log you have shared i see that the unisim libraries have been compiled succeessfully without any error messages.

 

Also, can you please elaborate more on why they seem to be empty?

 

 

 

 

Thanks & Regards,
Sravanthi B
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Observer
Observer
1,211 Views
Registered: ‎07-22-2013

Thanks for the reply. This turned out to be a simple path error on my part.  Or, too much work and not enough sleep!

View solution in original post

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Moderator
Moderator
1,204 Views
Registered: ‎09-15-2016

Hi @djmpap,

 

I am glad to know that you were able to resolve the issue. Can you please close this thread by marking your reply with resolution as accepted solution.

Thanks & Regards,
Sravanthi B
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