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Adventurer
Adventurer
10,022 Views
Registered: ‎08-24-2008

Changing compiler order for block design projects

Hi,

 

I have a block design project that makes use of the following:

1. AXI CDMA 

2. AXI Interconnect

3. AXI BRAM Controller (2)

4. BRAM (2)

 

I am using a AXI BFM to control the AXI CDMA during simulation (behavioral). However, I keep getting the following error:

 

"'blk_mem_gen_v8_2' is not compiled in library blk_mem_gen_v8_2 [D:/../../../project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/axi_bram_ctrl.vhd:431] "

 

I have searched other posts in this forum related to this error but none of them is useful to me. Only one has a workaround solution but that is not helping my case.

 

The only user written file is the testbench. The block design wrapper is good enough as top design file for me.

 

I suspect the error is because in the compilation step of axi_bram_ctrl.vhd it finds a reference to the block ram on line 431 but the bram has not yet been compiled.

 

In the attached screenshot, it can be seen that the axi_bram_ctrl module comes before blk_mem_gen. I have set hierarchy update to "automatic update and compile order". I am using Vivado 2014.4 (64 bit: SW Build 1071353, IP Build 1070531) on Windows 7.

 

I am wondering if there is a way to change the compile order of the source files are tool generated, I am unable to see them in the compile order dialog box. The compile order view of simulation files is attached.

 

I guess by changing the order it should be possible to get rid of this error.

 

Thanks!

bram_sim_error_vivado_simsources.jpg
compile_order_sim.jpg
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3 Replies
Moderator
Moderator
10,020 Views
Registered: ‎01-16-2013

Re: Changing compiler order for block design projects

Hello @sharad_snh,

 

Check the following ARs:

http://www.xilinx.com/support/answers/64112.html

 

http://www.xilinx.com/support/answers/57404.html

 

--Syed

 

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Adventurer
Adventurer
10,005 Views
Registered: ‎08-24-2008

Re: Changing compiler order for block design projects

Thanks Syed.

 

I have seen AR64112. I tried to use it but as you can see from the attached screen shot in my first message (the screen shot at the bottom), I am unable to see IP related source files in the simulation view under compile order. So, I am not able to change the compile order in GUI view. 

 

When I checked with 

get_files -compile_order sources -used_in simulation

I see that blk_mem_gen_v8_2.v is compiled at the very beginning. However, I am still getting the above error during simulation.

 

--Sharad

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Adventurer
Adventurer
9,996 Views
Registered: ‎08-24-2008

Re: Changing compiler order for block design projects

Hi Syed,

 

I figured out that the error was still there because of another issue with the testbench.

 

However, it would still be good to know if there is anyway of changing the compile order of the system generated files in a block design project.

 

Thanks for your help!

 

--Sharad

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