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Registered: ‎11-21-2013

Command "write_vhdl" with FIFO First-word-Fall-through causing simulation results mismatch

I am seriously troubled by using the "write_vhdl" command to generate a simulation file for FIFO Logic IP with FWFT mode.


I am using 2017.3, i just generated a fifo IP with 32 width and 256 depth with FWFT mode, and wrote a test bench just to write 256 words then read all of them out, with the Xsim and with the IP, the simulation is correct, I can see

it writes from 1 to 256 and reads out 1 to 256.


However, when I synthesize the IP and use write_vhdl fifo_sim.vhd to use this file for simulation, there are funny things happening.

With ZC706, It writes from 1 to 256 and reads out 3 to 256.

With ZCU102, it writes from 1 to 256 and reads out 2 to 256.


Did someone has the same experience? (I upload the project (Fifo_fallthrough_ip_test_ZC706 and *_n_ip_ZC706 test) the later one is using the file after write_vhdl.


If anyone wants to see the project in ZCU102, please comment.

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Registered: ‎04-24-2013


Hi @xubintan


I believe that you are not comparing equivalent Simulations.


When you simulate the results of the write_vhdl netlists you are running a functional simulation




If you run a Post Synthesis Functional simulation on the XCI version of the project then you see the same results





But if you run the Post Synthesis Timing Simulation then you are seeing different results as the timing data is taken into account





You can see that the sig_dout is no longer changing on the clock edge but slightly later, about 2.8ns.


Best Regards


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Registered: ‎11-21-2013

Hi, @amaccre,


Thank you for pointing this out, that is really cool.


But let's take a look at the figures you posted.


"Previously:  FWFT fifo, testbench writes sig_din = 1, 2, ..., 256"


The pre-synthesis behavior simulation ouputs the 1st value sig_dout = 2 at the rising edge of the clk

The post-synthesis functional ouputs the 1st value sig_dout = 2 at the rising edge of the clk,

the post-synthesis timing outputs the 1st value sig_dout = 1 around 1ns later after the rising edge of the clk


That is the real problem here, the behavior and functional simulation should output sig_dout = 1, no?


Thank you!


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