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Visitor itaychik
Visitor
3,514 Views
Registered: ‎01-17-2012

Compiling edk libraries in Modelsim 6.6d

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Hello all.

 

I have created a design in Vivado 2012.2 and wanted to simulate it in Modelsim 6.6d.

The design contains an embedded subsystem created in XPS, so to simulate it I first needed to compile edk libraries.

 

I used compile_simlib command in Vivado.

 

During compilation, I got a lot of errors.

 

For example:

 

** Error: /build/si10/EDK_P.28xd/env/Databases/IP3_hw_07161257/QA/P/EDK_P.28xd/output/export/processor/hardware/pcores/microblaze_v8_40_a/hdl/vhdl/address_data_hit.vhd: This version of the compiler is incompatible with the library .dat file.
** Error: /build/si10/EDK_P.28xd/env/Databases/IP3_hw_07161257/QA/P/EDK_P.28xd/output/export/processor/hardware/pcores/microblaze_v8_40_a/hdl/vhdl/address_data_hit.vhd(1): near "<byte 0x01>": illegal character found in source
** Error: /build/si10/EDK_P.28xd/env/Databases/IP3_hw_07161257/QA/P/EDK_P.28xd/output/export/processor/hardware/pcores/microblaze_v8_40_a/hdl/vhdl/address_data_hit.vhd(1): near "pÊ": Identifier may not contain non-graphic character.
** Error: /build/si10/EDK_P.28xd/env/Databases/IP3_hw_07161257/QA/P/EDK_P.28xd/output/export/processor/hardware/pcores/microblaze_v8_40_a/hdl/vhdl/address_data_hit.vhd(1): VHDL Compiler exiting



END_COMPILATION_MESSAGES(mti_se::microblaze_v8_40_a)
==============================================================================
compxlib[edk:microblaze_v8_40_a]: 1 error(s), 0 warning(s), 60.35 % complete

 

Does it mean that Modelsim 6.6d is not compatible with 14.2 and later tools?

 

I still tried to simulate it, but got the following error in Modelsim:

 

Loading unisim.rb36_internal_vhdl(rb36_internal_vhdl_v)
# ** Fatal: (vsim-7) Failed to open VHDL file "microblaze_0_bram_block_combined_0.mem" in rb mode.
# No such file or directory. (errno = ENOENT)
#    Time: 0 ps  Iteration: 0  Process: /mb_tb/mb_subsystem_i/microblaze_0_bram_block/microblaze_0_bram_block/ramb36e1_0/tdp/ramb36e1_tdp_inst/prcs_clk File: C:/Xilinx/14.2/ISE_DS/PlanAhead/data/vhdl/src/unisims/primitive/RAMB36E1.vhd
# FATAL ERROR while loading design

 

I'm not sure but maybe it's also related to edk libraries compilation problem.

 

Did anyone encountered similar problems and succeeded to solve them?

 

Thanks in advance.

 

Best regards,

 

Dima.

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Visitor apfitch
Visitor
4,223 Views
Registered: ‎05-28-2010

Re: Compiling edk libraries in Modelsim 6.6d

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Yes, you need a later version of Modelsim. Because part of the EDK Libraries is supplied in a compiled format (the .dat files you see in your errors), the correct version of Modelsim has to be used. I think you need any version starting with 10 (e.g. 10.0a up to 10.1d).

 

regards

Alan

 

P.S.  There was no Modelsim 7,8,9 - the numbering jumped from 6.6e to 10.0!

View solution in original post

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Visitor apfitch
Visitor
4,224 Views
Registered: ‎05-28-2010

Re: Compiling edk libraries in Modelsim 6.6d

Jump to solution

Yes, you need a later version of Modelsim. Because part of the EDK Libraries is supplied in a compiled format (the .dat files you see in your errors), the correct version of Modelsim has to be used. I think you need any version starting with 10 (e.g. 10.0a up to 10.1d).

 

regards

Alan

 

P.S.  There was no Modelsim 7,8,9 - the numbering jumped from 6.6e to 10.0!

View solution in original post

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