05-09-2019 01:04 AM
Simple question is when can we have that?
I want to use UVVM but cannot since Vivado has poor VHDL2008 support. Please look here - https://bitvis.no/dev-tools/uvvm/ and scroll down to the end of the webpage, where under Supported simulators one can see "Vivado: Awaiting proper VHDL 2008 support".
I cannot specify you a particular feature, but my reason is stated above!
05-16-2019 02:34 AM
Hi @dpaul24 ,
Unfortunately for complete VHDL-2008 support the simple answer is not soon and possibly not ever. It won't be available in the next release i.e. 2019.1.
Support for VHDL-2008 is being improved on a case by case basis and if you have a particular issue then it can be checked against what has already been requested.
If there is no prior request then it can be included in a Change Request.
05-16-2019 02:38 AM
Can you at least say when synthesis will align with simulation again? Currently synthesis has better VHDL2008 support (specifically unconstrained record types) than simulation.
Surely letting the two get out of alignment isnt really ideal?
05-16-2019 03:03 AM
Hi @richardhead ,
I honestly couldn't say. It is something that is being worked towards, it is on the roadmap but there is no fixed timeline.
As I provide tools support I cover both synthesis and simulation issues and this is something that I have pushed for and will continue to do so.
The reason that they are not in sync is that there are a finite number of engineers developing the tools and so VHDL-2008 issues tend to get fixed as they are reported and Change Requests are filed.
08-29-2019 04:53 AM
Let me make a request then: please add support to the simulator for sequential conditional assignments.
signal flag : boolean;
signal a,b,c,d : std_logic_vector;
c <= a when flag else b; -- allowed in both simulation and synthesis
process begin d <= a when flag else b; -- only allowed in synthesis ! end process;
08-29-2019 06:12 AM
dont hold your breath , its VHDL.
It appears Xilinx are slowly dropping support for VHDL,
or lets say , not putting much resource into it,
Bottom line, the people in Xilinx USA seem to mainly use Linux and versions of Verilog,
Look at the VHDL 87 style templates still provided in vivado 2019.1
One day they will ask the community to update them for them !!
11-20-2019 01:35 AM
I am just writing to let you XIlinx know,that I would as well love to see VHDL 2008 standard supported in simulation.
Its 11 years since it was announced and its still not implemeted. I believe that it should have been already by this time.
Take an example for the various C++ standards and their support in Microsoft Visual Studio for instance. They are behind the available standards, but as far as I know, its definitely not 11 years.
11-22-2019 12:59 AM
Can you please add automatic condition converter from standard_logic to bool, please?
signal A, B : std_logic;
if A and B then ...
VHDL is widely popular, especially in Europe and we would really appriciate having core VHDL-2008 features supported for both synthesis and simulation as it has been over 10 years since standard came out.
In the last years OSVVM and UVVM have also got closer to Verilog/SV verification methodologies and would like to see them supported in the feature Vivado.
11-22-2019 01:38 AM
Since I see this thread alive again this morning....
@all who have been fighting for better VHDL2008 support..........
Sometimes while you use this forum you are requested to take a survey. I request you all to spare some time and take it. Then please focus on the part/s where you can submit your comments/suggestions/etc and there in, pitch your vote for more VHDL2008 support.
Maybe by this way our requests get heard.