05-09-2019 01:04 AM
Simple question is when can we have that?
I want to use UVVM but cannot since Vivado has poor VHDL2008 support. Please look here - https://bitvis.no/dev-tools/uvvm/ and scroll down to the end of the webpage, where under Supported simulators one can see "Vivado: Awaiting proper VHDL 2008 support".
I cannot specify you a particular feature, but my reason is stated above!
05-16-2019 02:34 AM
Hi @dpaul24 ,
Unfortunately for complete VHDL-2008 support the simple answer is not soon and possibly not ever. It won't be available in the next release i.e. 2019.1.
Support for VHDL-2008 is being improved on a case by case basis and if you have a particular issue then it can be checked against what has already been requested.
If there is no prior request then it can be included in a Change Request.
05-16-2019 02:38 AM
Can you at least say when synthesis will align with simulation again? Currently synthesis has better VHDL2008 support (specifically unconstrained record types) than simulation.
Surely letting the two get out of alignment isnt really ideal?
05-16-2019 03:03 AM
Hi @richardhead ,
I honestly couldn't say. It is something that is being worked towards, it is on the roadmap but there is no fixed timeline.
As I provide tools support I cover both synthesis and simulation issues and this is something that I have pushed for and will continue to do so.
The reason that they are not in sync is that there are a finite number of engineers developing the tools and so VHDL-2008 issues tend to get fixed as they are reported and Change Requests are filed.
08-29-2019 04:53 AM
Let me make a request then: please add support to the simulator for sequential conditional assignments.
signal flag : boolean;
signal a,b,c,d : std_logic_vector;
c <= a when flag else b; -- allowed in both simulation and synthesis
process begin d <= a when flag else b; -- only allowed in synthesis ! end process;
08-29-2019 06:12 AM
dont hold your breath , its VHDL.
It appears Xilinx are slowly dropping support for VHDL,
or lets say , not putting much resource into it,
Bottom line, the people in Xilinx USA seem to mainly use Linux and versions of Verilog,
Look at the VHDL 87 style templates still provided in vivado 2019.1
One day they will ask the community to update them for them !!
11-20-2019 01:35 AM
I am just writing to let you XIlinx know,that I would as well love to see VHDL 2008 standard supported in simulation.
Its 11 years since it was announced and its still not implemeted. I believe that it should have been already by this time.
Take an example for the various C++ standards and their support in Microsoft Visual Studio for instance. They are behind the available standards, but as far as I know, its definitely not 11 years.
11-22-2019 12:59 AM
Can you please add automatic condition converter from standard_logic to bool, please?
signal A, B : std_logic;
if A and B then ...
VHDL is widely popular, especially in Europe and we would really appriciate having core VHDL-2008 features supported for both synthesis and simulation as it has been over 10 years since standard came out.
In the last years OSVVM and UVVM have also got closer to Verilog/SV verification methodologies and would like to see them supported in the feature Vivado.
11-22-2019 01:38 AM
Since I see this thread alive again this morning....
@all who have been fighting for better VHDL2008 support..........
Sometimes while you use this forum you are requested to take a survey. I request you all to spare some time and take it. Then please focus on the part/s where you can submit your comments/suggestions/etc and there in, pitch your vote for more VHDL2008 support.
Maybe by this way our requests get heard.
01-13-2020 05:51 AM
so ... looks like the future is SystemVerilog ... ? If so, it will be a disaster for all VHDL programmers and code bases out there, but at least Xilinx should be clear on this, so we know at least where things are going to, and we can start anticipating to that.
01-13-2020 06:10 AM
And... hasn't VHDL 2019 recently been ratified?
Where is this on Xilinx's roadmap?
Once 2008 is done I suppose? :)
01-13-2020 07:02 AM
01-13-2020 07:42 AM - edited 01-13-2020 07:50 AM
b) Spend a few million on parts, and then talk to your local friendly FAE.
More like threaten not to spend a few million on parts and go to intel because of the lack of support. Probably how synthesis got its decent 2008 support :)
And... hasn't VHDL 2019 recently been ratified?
Yes. But unless big customers start using VHDL for verification (alot use SV) AND use the Vivado Simulator (most dont, because modelsim/activeHDL are better) then keep on waiting. Probably best giving GHDL a try or even gettting the intel webpack a go (it comes with modelsim!). Xilinx are pushing hard with Vitis, and looking at Versal, they are starting to look similar in architecture to what intel had on their roadmap several years ago (wouldnt be surprised if OpenCL made an appearance soon too).
06-13-2020 01:40 PM
It's my first time posing here in a while (took a detour with Intel/Quartus). I would say that Xilinx's support for VHDL 2008 is way beyond Intel's (in that as of the Lite version of Quartus 19.1 they don't support it at all). I did find it odd that Xilinx went to the effort to support close to a proper subset of VHDL2008 for synthesis but neglected simulation (which is arguably easier). It would have been convenient if the synthesizer could maybe post warnings that <VHDL 2008 conditional assignment> etc is not supported in Xilinx simulation.
A couple of solutions for people who want both VHDL 2008 for bitstream and test benches. Can install Quartus Lite 19.1 and use the free Modelsim that comes with it. Or, in my case, I'm lucky enough to have a license for ModelSim-SE. Use that instead. You will need to precompile the Xilinx libraries which (on the webpack version of Vivado) takes more than 1 hour even on a high-end desktop. The alternative, which is tedious and pointless, would be to rewrite the bits of VHDL2008 the Vivado Simulator can't handle.