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Scholar dpaul24
Scholar
1,011 Views
Registered: ‎08-07-2014

Complete VHDL2008 support in Vivado

Simple question is when can we have that?

I want to use UVVM but cannot since Vivado has poor VHDL2008 support. Please look here - https://bitvis.no/dev-tools/uvvm/ and scroll down to the end of the webpage, where under Supported simulators one can see "Vivado: Awaiting proper VHDL 2008 support".

 

@hemangd, Reference thread - https://forums.xilinx.com/t5/Synthesis/Xilinx-roadmap-for-VHDL-support/m-p/970631#M30987

I cannot specify you a particular feature, but my reason is stated above!

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13 Replies
Highlighted
Moderator
Moderator
967 Views
Registered: ‎04-24-2013

Re: Complete VHDL2008 support in Vivado

Hi @dpaul24 ,

Unfortunately for complete VHDL-2008 support the simple answer is not soon and possibly not ever. It won't be available in the next release i.e. 2019.1.

Support for VHDL-2008 is being improved on a case by case basis and if you have a particular issue then it can be checked against what has already been requested.

If there is no prior request then it can be included in a Change Request.

Best Regards
Aidan

 

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Scholar richardhead
Scholar
965 Views
Registered: ‎08-01-2012

Re: Complete VHDL2008 support in Vivado

@amaccre 

Can you at least say when synthesis will align with simulation again? Currently synthesis has better VHDL2008 support (specifically unconstrained record types) than simulation.

Surely letting the two get out of alignment isnt really ideal?

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Moderator
Moderator
959 Views
Registered: ‎04-24-2013

Re: Complete VHDL2008 support in Vivado

Hi @richardhead ,

I honestly couldn't say. It is something that is being worked towards, it is on the roadmap but there is no fixed timeline.

As I provide tools support I cover both synthesis and simulation issues and this is something that I have pushed for and will continue to do so.

The reason that they are not in sync is that there are a finite number of engineers developing the tools and so VHDL-2008 issues tend to get fixed as they are reported and Change Requests are filed.

Best Regards
Aidan

 

 

 

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Scholar vanmierlo
Scholar
707 Views
Registered: ‎06-10-2008

Re: Complete VHDL2008 support in Vivado

Let me make a request then: please add support to the simulator for sequential conditional assignments.

signal flag : boolean;
signal a,b,c,d : std_logic_vector;
c <= a when flag else b; -- allowed in both simulation and synthesis
process begin     d <= a when flag else b; -- only allowed in synthesis ! end process;

Maarten

Teacher drjohnsmith
Teacher
694 Views
Registered: ‎07-09-2009

Re: Complete VHDL2008 support in Vivado

dont hold your breath , its VHDL.

 

It appears Xilinx are slowly dropping support for VHDL,

    or lets say , not putting much resource into it,

 

Bottom line, the people in Xilinx USA seem to mainly use Linux and versions of Verilog,

   (

      Look at the VHDL 87 style templates still provided in vivado 2019.1

     One day they will ask the community to update them for them !!

   )

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Observer aenerine
Observer
455 Views
Registered: ‎04-27-2017

Re: Complete VHDL2008 support in Vivado

Hi,

I am just writing to let you XIlinx know,that I would as well love to see VHDL 2008 standard supported in simulation.

Its 11 years since it was announced and its still not implemeted. I believe that it should have been already by this time.

Take an example for the various C++ standards and their support in Microsoft Visual Studio for instance. They are behind the available standards, but as far as I know, its definitely not 11 years.

Thanks  

Newbie anzejakos
Newbie
412 Views
Registered: ‎06-13-2019

Re: Complete VHDL2008 support in Vivado

Can you please add automatic condition converter from standard_logic to bool, please?

signal A, B : std_logic;
...

if A and B then ...

Guys, c'mon!

VHDL is widely popular, especially in Europe and we would really appriciate having core VHDL-2008 features supported for both synthesis and simulation as it has been over 10 years since standard came out. 

In the last years OSVVM and UVVM have also got closer to Verilog/SV verification methodologies and would like to see them supported in the feature Vivado.

Scholar dpaul24
Scholar
402 Views
Registered: ‎08-07-2014

Re: Complete VHDL2008 support in Vivado

Since I see this thread alive again this morning....

@all who have been fighting for better VHDL2008 support..........

Sometimes while you use this forum you are requested to take a survey. I request you all to spare some time and take it. Then please focus on the part/s where you can submit your comments/suggestions/etc and there in, pitch your vote for more VHDL2008 support.

Maybe by this way our requests get heard.

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Advisor ronnywebers
Advisor
177 Views
Registered: ‎10-10-2014

Re: Complete VHDL2008 support in Vivado

so ... looks like the future is SystemVerilog ... ? If so, it will be a disaster for all VHDL programmers and code bases out there, but at least Xilinx should be clear on this, so we know at least where things are going to, and we can start anticipating to that. 

** kudo if the answer was helpful. Accept as solution if your question is answered **
Explorer
Explorer
169 Views
Registered: ‎06-25-2014

Re: Complete VHDL2008 support in Vivado

And... hasn't VHDL 2019 recently been ratified?

 

Where is this on Xilinx's roadmap?

 

Once 2008 is done I suppose? :)

 

 

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Newbie anzejakos
Newbie
164 Views
Registered: ‎06-13-2019

Re: Complete VHDL2008 support in Vivado

How can we even open case or feature request for new VHDL2008 features?

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Teacher drjohnsmith
Teacher
143 Views
Registered: ‎07-09-2009

Re: Complete VHDL2008 support in Vivado

Based upon previous experience only.

options are

a) Start a campaign on the forums ( very difficult as the threads drop off the front screen very quickly )

b) Spend a few million on parts, and then talk to your local friendly FAE.

c) pray to your god.
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Scholar richardhead
Scholar
130 Views
Registered: ‎08-01-2012

Re: Complete VHDL2008 support in Vivado

@drjohnsmith 

b) Spend a few million on parts, and then talk to your local friendly FAE.

More like threaten not to spend a few million on parts and go to intel because of the lack of support. Probably how synthesis got its decent 2008 support :)

@andrewlan 

And... hasn't VHDL 2019 recently been ratified?

Yes. But unless big customers start using VHDL for verification (alot use SV) AND use the Vivado Simulator (most dont, because modelsim/activeHDL are better) then keep on waiting. Probably best giving GHDL a try or even gettting the intel webpack a go (it comes with modelsim!). Xilinx are pushing hard with Vitis, and looking at Versal, they are starting to look similar in architecture to what intel had on their roadmap several years ago (wouldnt be surprised if OpenCL made an appearance soon too).