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5,138 Views
Registered: ‎08-09-2012

Core "Multiply Accumulator" simulation not working

 

Im trying to simulate the behaviour of this XILINX IPCORE (Multiplier Accumulator, from BaseIP), in order to use it a more complex desing. 

I need a 16bit signed inputs and 16bit output with the internal acc above 33. I had created a small Tb in order to do simple test. Here is my tb code, and the output in ISE and Modelsim.

 

But the CORE output, the wire s, never changes. I dont understand what is going on here. Documentation of the core says that this core doesn't have a behavioral model for verilog, just Verilog UniSim structural model. Maybe that is the problem, but I think the simulation must be performed correctly with this model on ModelSim.

 

My code.

 

`timescale 1ns / 1ps

module tb_ejemplo_mult;


reg clk;
reg ce;
reg sclr;
wire [15:0] s;
reg [15:0] a;
reg [15:0] b;
wire clk1;
wire ce1;
wire sclr1;
wire [15:0] a1;
wire [15:0] b1;

assign clk1 = clk;
assign ce1 = ce ;
assign sclr1 = sclr;
assign a1 = a;
assign b1 = b;


mult mult_0 (
.clk(clk1), // input clk
.ce(ce1), // input ce
.sclr(sclr1), // input sclr
.s(s), // input [15 : 0] a
.a(a1), // input [15 : 0] b
.b(b1) // output [15 : 0] s
);

always #10 clk <= !clk;

initial begin
clk = 1'b0;
ce= 1'b0;
sclr =1'b1;
#100
a=16'd5;
b=16'd3;
sclr =1'b0;
#100
ce=1'b1;
#100
a=16'd2;
b=16'd4;
end
endmodule

 

-----------------------------------------

 

ISE console output. 

 

Regenerate Core - mult: All required files are available.

Process "Regenerate Core" completed successfully

Started : "Simulate Behavioral Model".


Creating automatic do files...
----------------------------------------------------------------------------
* udo file already exist (tb_ejemplo_mult.udo). It will not be re-generated.
* creating main do file (tb_ejemplo_mult.fdo) for Behavioral Simulation...
> executing 'D:/Herramientas/Mentor/modeltech_6.6d/win32/vsim.exe -version' to get the mti_se version...
> mti_se version is 6.6d
* determining pre-compiled simulation library path information...
> using mapping file set by MODELSIM env (D:\Herramientas\Mentor\modeltech_6.6d\modelsim.ini)...
> extracting library mapping information from 'D:\Herramientas\Mentor\modeltech_6.6d\modelsim.ini'...
> Compilation info: secureip
********************************************************
+ Source Library : D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/secureip/mti
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 0
********************************************************
> secureip (=>"D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/verilog/mti_se/6.6d/nt64/secureip")
> Compilation info: unisim
********************************************************
+ Source Library : D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/vhdl/src/unisims/secureip
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 0
********************************************************
********************************************************
+ Source Library : D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/vhdl/src/unisims
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 0
********************************************************
> unisim (=>"D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/vhdl/mti_se/6.6d/nt64/unisim")
> Compilation info: unimacro
********************************************************
+ Source Library : D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/vhdl/src/unimacro
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 0
********************************************************
> unimacro (=>"D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/vhdl/mti_se/6.6d/nt64/unimacro")
> Compilation info: unisims_ver
********************************************************
+ Source Library : D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/verilog/src/unisims
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 0
********************************************************
> unisims_ver (=>"D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/verilog/mti_se/6.6d/nt64/unisims_ver")
> Compilation info: unimacro_ver
********************************************************
+ Source Library : D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/verilog/src/unimacro
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 0
********************************************************
> unimacro_ver (=>"D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/verilog/mti_se/6.6d/nt64/unimacro_ver")
> Compilation info: simprim
********************************************************
+ Source Library : D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/vhdl/src/simprims/secureip/mti
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 0
********************************************************
********************************************************
+ Source Library : D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/vhdl/src/simprims
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 0
********************************************************
> simprim (=>"D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/vhdl/mti_se/6.6d/nt64/simprim")
> Compilation info: simprims_ver
********************************************************
+ Source Library : D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/verilog/src/simprims
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 0
********************************************************
> simprims_ver (=>"D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/verilog/mti_se/6.6d/nt64/simprims_ver")
> Compilation info: xilinxcorelib
********************************************************
+ Source Library : D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/vhdl/src/XilinxCoreLib
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 323
********************************************************
> xilinxcorelib (=>"D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/vhdl/mti_se/6.6d/nt64/xilinxcorelib")
> Compilation info: xilinxcorelib_ver
********************************************************
+ Source Library : D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/verilog/src/XilinxCoreLib
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 1
********************************************************
> xilinxcorelib_ver (=>"D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/verilog/mti_se/6.6d/nt64/xilinxcorelib_ver")
> Compilation info: edk
********************************************************
+ Source Library : D:\Herramientas\Xilinx\13.3\ISE_DS\EDK/hw
+ Compilation Time : Thu Aug 09 15:21:23 2012
+ Platform : nt64
+ Simulator : mti_se
+ Simulator Version : 6.6d
+ Xilinx Version : 13.3
+ Number of Errors : 0
+ Number of Warnings: 264
********************************************************
> edk (=>"D:/Herramientas/Xilinx/13.3/ISE_DS/ISE/mti_se/6.6d/nt64/edk")
* wave file already exists (tb_ejemplo_mult_wave.fdo), It will not be re-generated.
* writing display options...
----------------------------------------------------------------------------
INFO: Automatic do files created successfully.

Launching Modelsim GUI...
Modelsim GUI launched successfully
Process Simulate Behavioral Model setup completed successfully, the GUI will be up in a moment.

 

-------------------------------------

 

ModelSim output

 

# vsim -do \{do \{tb_ejemplo_mult.fdo\}\}
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: (vopt-19) Failed to access library 'work.{tb_ejemplo_mult' at "work.{tb_ejemplo_mult".
# No such file or directory. (errno = ENOENT)
# ** Error: Library work.{tb_ejemplo_mult not found.
# Error loading design
do tb_ejemplo_mult.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.6d Compiler 2010.11 Nov 1 2010
# -- Compiling module mult
# -- Compiling module glbl
#
# Top level modules:
# mult
# glbl
# Model Technology ModelSim SE vlog 6.6d Compiler 2010.11 Nov 1 2010
# -- Compiling module tb_ejemplo_mult
#
# Top level modules:
# tb_ejemplo_mult
# Model Technology ModelSim SE vlog 6.6d Compiler 2010.11 Nov 1 2010
# -- Compiling module glbl
#
# Top level modules:
# glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -L secureip -lib work -voptargs=\"+acc\" -t 1ps work.tb_ejemplo_mult glbl
# ** Note: (vsim-3812) Design is being optimized...
# Loading work.tb_ejemplo_mult(fast)
# Loading work.mult(fast)
# Loading unisims_ver.GND(fast)
# Loading unisims_ver.VCC(fast)
# Loading unisims_ver.DSP48E(fast)
# Loading work.glbl(fast)
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body.tree

 

 

wave.jpg
0 Kudos
4 Replies
Teacher eilert
Teacher
5,122 Views
Registered: ‎08-14-2007

Re: Core "Multiply Accumulator" simulation not working

Hi,

not sure if I understood this correctly:

you are using 16 bit inputs, and from the normally resulting 33 bits you took 16 bits for the output. But which ones?

The MSBs? In that case, if you feed such small values in your testbench the result has to be 0 since you aren't getting into the region where a result can be seen.

Use some significantly bigger values in your testbench if my assumption was correct and there should appear something in your s output.

 

Using a structural model schould make no difference for the result, just might use some more computing ressources due to its bigger complexity compared to a behavioral model.

 

Also be prepared for some latency before the result appears. This can be found in the IP-core setting.

 

Have a nice simulation

  Eilert

 

 

0 Kudos
5,117 Views
Registered: ‎08-09-2012

Re: Core "Multiply Accumulator" simulation not working

Hello again.

Eilert thanks, you are right. I asumed that the CORE returns the bits from [16:0] and I was wrong. I simulated again using one output of same width as the accumulator and now everything its ok.

The problem for me now is how to fit again the 32 bit array to a 16bit one, in order to do the same as my C reference code does.

short a;
short b;
short c = (a * b) + acc;

I have to find how C manage this, but now my HDL issue is solved, thanks again

0 Kudos
Teacher eilert
Teacher
5,106 Views
Registered: ‎08-14-2007

Re: Core "Multiply Accumulator" simulation not working

Hi,

you can find out about the behavior of your C code quite easily.

Write a small C-Testbench and generate a number of results over a wide input range.

You will then see what range of input values can be used before the output creates wrong results.

 

When you do the same calculations with long-type variables, your testbench should be able to detect wrong results automatically.

 

Have a nice simulation

  Eilert

0 Kudos
5,102 Views
Registered: ‎08-09-2012

Re: Core "Multiply Accumulator" simulation not working

Hello,

 

That is what I was doing more or less. Im working with integer operators to compute and interpolate 8bit pixels. So after all operations I have to CLIP to a value between 0xFFh : 0x00h. Im trying to use the less possible bits in the data path without losing the correct values.

 

Thanks again, Yeray. 

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