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Visitor krayzzee
Visitor
3,092 Views
Registered: ‎08-15-2012

Create *_par.prj for simulation

Hi,

 

I want to generate  simulation executables for par simulation but after place and route ISE is not generating a *_par.prj which fuse requires to create simulation executable. How can I create this *_par.prj from command line ( GUI automatically creates it when running simulation but I want to create it from command line )  and update it automatically after each par .

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2 Replies
Xilinx Employee
Xilinx Employee
3,083 Views
Registered: ‎04-16-2012

Re: Create *_par.prj for simulation

Hi,

 

Follow the steps under the section "running timing simulation of a VHDL/Verilog design from the command line" of isim user guide at http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/plugin_ism.pdf 

 

Thanks.

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Xilinx Employee
Xilinx Employee
3,076 Views
Registered: ‎07-16-2008

Re: Create *_par.prj for simulation

A .prj used for timing simulation typically includes top_timesim.v/vhd (which is the post-PAR simulation model), testbench as well as glbl.v (in verilog case).

 

The *_timesim.v/vhd is generated by netgen and located at <project dir>/netgen/par.

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