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Visitor
Visitor
3,065 Views
Registered: ‎07-03-2017

Disabled Simulation Option

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Hi,

 

 

I have two questions.

 

 

Firstly, I am trying to make a 4 bit counter on Vivado 14.3. I have realized that when i tried to simulate the VHDL code, the "Run Post-Synthesis Functional Simulation" and "Run Post-Synthesis Timing Simulation" options are disabled. Do you have any idea to enable them or is this a normal situation? I have shown below.

 

 

xilinxforum.jpg

 

 

 

My second question is related to that when i am trying to add source, the "Next" button is disabled also. Do you have an idea about this or is it a normal situation. I have shown below.

 

 

xilinxforum2.jpg

 

 

Thank you.

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Moderator
Moderator
5,258 Views
Registered: ‎06-05-2013
For the first one. Have you synthesized your design? If not then first synthesize the design then those options will be enabled.

For the second one:
Have you selected the add files/ add directories/ create file. If you see all the files there then just click on finish. Once you select any of the options mentioned you will be able to see the respective next options.
Thanks
HJ
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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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Highlighted
Moderator
Moderator
5,259 Views
Registered: ‎06-05-2013
For the first one. Have you synthesized your design? If not then first synthesize the design then those options will be enabled.

For the second one:
Have you selected the add files/ add directories/ create file. If you see all the files there then just click on finish. Once you select any of the options mentioned you will be able to see the respective next options.
Thanks
HJ
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

Highlighted
Xilinx Employee
Xilinx Employee
3,013 Views
Registered: ‎08-01-2008
check this ARs
https://www.xilinx.com/support/answers/63987.html

For ISE flow check this ARs
https://www.xilinx.com/support/answers/45668.html
Thanks and Regards
Balkrishan
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