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grenoble2007
Visitor
Visitor
4,085 Views
Registered: ‎02-04-2009

EDK 92 vsim unisims_ver and verilog fails to simulate

Hi,

I would like to simulate a design made with EDK 92i (SP2)  of ml405 based basic design

Unfortunately, the simulation fails du to the verilog module of the MPMC

 

I make a configuration of the top level that includes the design and here is the message I have 

# vsim -L unisims_ver -L simprims_ver work.bench_cfg
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: /rech-fmr/mancini/EDK92/lib/ise92/unisims_ver/unisims_ver_source.v(60928): Failed to find 'glbl' in hierarchical name.
# Optimization failed

 

What's the trouble ?

Does it mean that unisms_ver_source.v is different from the VHDL code ????

What should I do to simulate this design ?

Thanks 

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edv
Xilinx Employee
Xilinx Employee
4,069 Views
Registered: ‎08-15-2007

Hello,

 

To resolve this issue, make sure the globals source file is compiled.  This source file is located at:

 

%XILINX%/verilog/src/glbl.v

 

Edit your simulation script to the source code above is compiled.  It should resolve the error.

 

Hope this helps.

Eddie
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