12-17-2018 04:41 AM
I'm using vivado 2018.3 and I created a custom IP withe the IP manager.
When i try to launch my simulation I have this error:
INFO: [Vivado 12-5682] Launching behavioral simulation in 'z:/developement/vhdl/ip_repo/edit_axi_pwm_v1_0.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Tb_Pwm' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'z:/developement/vhdl/ip_repo/edit_axi_pwm_v1_0.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Tb_Pwm_vhdl.prj"
ERROR: [XSIM 43-3268] Logical library name '"../../../../axi_pwm_1.0/hdl/axi_pwm_v1_0.vhd"' should not contain white space, new line, /, \, = or .
ERROR: [XSIM 43-3217] Tb_Pwm_vhdl.prj (line 3): Incorrect project file syntax. Correct syntax is one of: vhdl <worklib> <file>, verilog <worklib> <file> [<file> ...] [[-d <macro>] ...] [[-i <include>] ...], or NOSORT. Presence of NOSORT on a line of its own disables file order sorting.
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'Z:/developement/VHDL/ip_repo/edit_axi_pwm_v1_0.sim/sim_1/behav/xsim/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'Z:/developement/VHDL/ip_repo/edit_axi_pwm_v1_0.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
ipx::merge_project_changes files [ipx::current_core]
WARNING: [IP_Flow 19-5226] Project source file 'z:/developement/VHDL/ip_repo/axi_pwm_1.0/component.xml' ignored by IP packager.
I just don't understand why it complains about the syntax of the files names...
12-19-2018 12:41 AM
Can you please share the archived project to check this issue at our end.
12-19-2018 12:48 AM
12-28-2018 03:45 PM - edited 12-28-2018 03:48 PM
I just ran into the same problem. I noticed a couple of potential issues with the generated .prj passed to xvhdl:
# compile vhdl design source files vhdl \ "../../../../omw_test_1.0/hdl/omw_test_v1_0_S_AXI.vhd" \ "../../../../omw_test_1.0/hdl/omw_test_v1_0.vhd" \ # Do not sort compile order nosort
1) There are three consecutive spaces immediately following the vhdl directive, where the work library argument should seemingly appear.
2) UG900 specifies that only a single source file can be passed per line with the vhdl directive (as opposed to the verilog directive).
I tried fixing up the .prj file manually, but since it gets automatically regenerated and overwritten every time you hit the "Run Simulation" action, it didn't help.
12-28-2018 08:25 PM
Update: Editing the "LIBRARY" property for the .vhd sources, and changing it from its default of blank/empty, resolved this issue for me.
12-28-2018 10:14 PM
Thanks for the tip on setting the library property, this worked for me as well.
01-22-2019 10:58 AM
04-01-2019 06:56 AM
It seems to be necessary to apply this setting each time the project is re-opened in IP Packager.
09-06-2019 03:21 AM
Very helpful and also fixed this annoying bug. Xilinx please fix.
09-23-2019 08:30 AM
Thanks for the library hint. I my case I changed it from blank to xil_defaultlib and it did the trick.
12-05-2019 09:47 AM
Thank you very much. This worked for me too. In my case, I also had change to "xil_defaultlib" for all nested verilog source files.
01-30-2020 02:50 PM
This worked for me also, but it is seriously annoying and takes about 15 minutes to go through all of the files in my design to change this. Is there a global way to change all the files in a hierarch without having to go to each file and change it? I Haven't found anything.
01-30-2020 02:52 PM
is there any way to globally set the library?
Currently we need to modify every file in the custom RTL hierarchy, takes about 20 min any time we want to make a change and simulate the change before moving back up to the top level
01-31-2020 01:21 AM