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Nico5
Newbie
Newbie
843 Views
Registered: ‎10-20-2020

ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/fft32_tb_behav/obj/xsim_1.c.

Hello.

I am new in VIVADO and VIVADO HLS, and I am having troubles in "Simulation" stage.

The Message console says [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/nicolas/Documents/VIVADO/FFT_32/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log' file for more information, then I opened the elaborate.log file and found the error in the title.

I attached my xsim_1.c file.

I am running VIVADO 2019.2 on Ubunt 20.04.

Thanks!

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5 Replies
sunilku
Xilinx Employee
Xilinx Employee
802 Views
Registered: ‎08-10-2015

Hi @Nico5 ,

 

Can you please share the design for further debug.

 

Thanks,

Sunilkumar

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Nico5
Newbie
Newbie
785 Views
Registered: ‎10-20-2020

Hi @sunilku , thanks for your help!

I am not sure which is the file that contains the design, but there is design_1.tcl file and I hope this is the one.

In order to resolve the issue, I append ftt.cpp, this is a file that I use in VIVADO HLS to create an IP_Core, and datasrc.v, datasrc_tb.v.

Thanks!

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Nico5
Newbie
Newbie
777 Views
Registered: ‎10-20-2020

@sunilkuI have open and example project and the I tried to run the simulation, in order to verify if my design was bad, but there was the same issue.

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sunilku
Xilinx Employee
Xilinx Employee
729 Views
Registered: ‎08-10-2015

hi @Nico5 ,

 

With the shared files, I am not able to reproduce the issue. Can you please share the generated Vivado project if possible?

And also please share the OS details also.

 

Thanks,

Sunilkumar

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harikade
Xilinx Employee
Xilinx Employee
606 Views
Registered: ‎05-01-2019

Hi,

Please try running design by adding the switch '-cc clang' to xelab command.

Thanks,

Harika.

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