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squaringcircle
Adventurer
Adventurer
1,625 Views
Registered: ‎12-19-2018

ERROR: [XSIM 43-4316] Can not find file: C:/Users/ref/AppData/Roaming/Xilinx/Vivado/class HDDASrcFile * __ptr64

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Hi Forum,

 

I'm trying to simulate a Block design for a DDR3 controller using a 1G x 8 Micron component.

I've downloaded the model from Micron and attached it to the top level simulation in my project.

Once I instantiate the ddr3 component, simulation fails with the following error message:

 

"ERROR: [XSIM 43-4316] Can not find file: C:/Users/ref/AppData/Roaming/Xilinx/Vivado/class HDDASrcFile * __ptr64"

 

I found 2 entries in the forum on this topic, but they don't seem to match the issue.

 

I've already implemented/simulated other DDR3 components from Micron without facing major issues.

As a note - the project I'm working on is coming from a colleague, I'm jsut adding the DDR3 controller.

 

Thanks for any advice in advance.

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squaringcircle
Adventurer
Adventurer
1,542 Views
Registered: ‎12-19-2018

Hi again,

 

After some debugging, I found out this is related to a file acces done by the DDR3 model from micron to a non-existing folder.

After manually creating the folder and editing the full path - not relative - the basic simulation setup is working now.

 

Thanks for all inputs so far.

View solution in original post

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bandi
Moderator
Moderator
1,600 Views
Registered: ‎09-15-2016

Hi @squaringcircle,

I hope you are referring to the below posts:

https://forums.xilinx.com/t5/Simulation-and-Verification/ERROR-XSIM-43-4316/m-p/800136

https://forums.xilinx.com/t5/Simulation-and-Verification/Error-Message-in-Vivado-2017-2-can-not-find-file-class/m-p/789988/highlight/true

Can you please recheck your RTL modules in your design. Also, was the design simulating before adding the DDR3 controller?

If the issue occurs only after instantiating DDR3 controller, then can you please check if you have instantiated it correctly.

 

Thanks & Regards,
Sravanthi B
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squaringcircle
Adventurer
Adventurer
1,581 Views
Registered: ‎12-19-2018

Thanks for your quick response.

 

The error only occurs after I instantiate the following block:

 

//DDR3 component instantiation
    ddr3 ddr3_component_a (
       .rst_n(ddr3a_reset_n),
       .ck(ddr3a_ck),
       .ck_n(ddr3a_ck_N),
       .cke(ddr3a_cke),
       .cs_n(ddr3a_cs_n),
       .ras_n(ddr3a_ras_n),
       .cas_n(ddr3a_cas_n),
       .we_n(ddr3a_we_n),
       .dm_tdqs(ddr3a_dm),
       .ba(ddr3a_ba),
       .addr(ddr3a_a),
       .dq(ddr3a_dq),
       .dqs(ddr3a_dqs),
       .dqs_n(ddr3a_dqs_N),
       .tdqs_n(),
       .odt(ddr3a_odt)
    );

 

This is basically the external DDR3 component. I couldn't find any particular error in the instantiation.

The model was provided by Micron, and I'm using it unmodified.

The only thing I changed in the project - I've set the DDR3 model from Micron to be a SystemVerilog file, as they're using features not supported by verilog.

 

Does that help somehow?

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squaringcircle
Adventurer
Adventurer
1,543 Views
Registered: ‎12-19-2018

Hi again,

 

After some debugging, I found out this is related to a file acces done by the DDR3 model from micron to a non-existing folder.

After manually creating the folder and editing the full path - not relative - the basic simulation setup is working now.

 

Thanks for all inputs so far.

View solution in original post

0 Kudos