04-15-2018 10:50 PM
I'm working on filter design on Vivado 2017.4. I'm using DDS for generating sine wave and giving it to FIR compiler .
When I tried simulating , I'm getting the error which I'm attaching in the snapshot below.
Can u please help me out in solving this error.
Thanks and regards,
04-15-2018 11:09 PM
Please share the project or test case to look into this further. Also try in latest tool version 2018.1 once.
04-15-2018 11:14 PM
Can you please check if the following posts helps:
Thanks & Regards,
04-15-2018 11:49 PM
I tried changing the clock stimulus but it didn't work.
The valid signal to fir compiler is given from dds compiler and the files are encrypted in IP.
I'll be sharing the project files soon.
Thanks and regards,
04-16-2018 04:55 AM
File test_design_fir.v is missing from the shared project. Because of the missing file we can't move further. So, can you please share the complete archived project. To archive the project click on File --> Archive Project in Vivado
04-16-2018 11:27 PM
It looks the M_AXIS_PHASE_0_tready is not initialized.
I tried to assign an initial value to it in the testbench and the error was not seen.
wire M_AXIS_PHASE_0_tready = 1'b1;
05-13-2019 08:38 AM
Interesting. Is there a way for Xilinx to make that error traceable? I was able to quickly resolve through this thread, but the error itself can't be traced. I found it after I added tready to an axis interface and forgot to hook it up. Same error.
Thanks for the post providing a quick solution.
05-13-2019 05:07 PM
05-13-2019 05:57 PM
Yes I understand where it came from, and it was clear from your analalysis of the OP's code how to correct the simulation failure. All I am saying is that this simulation failure didn't trace to an obvious and simple solution. I ask that Xilinx considering providing the traceability to ease debug.
05-13-2019 06:36 PM
The IP source is encrypted and therefore not traceable.
We can document an answer though, to provide the solution to this error and avoid duplicate effort.