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Participant
Participant
5,362 Views
Registered: ‎02-19-2018

ERROR:add_1 must be in range [-1,DEPTH-1]

Hi,

I'm working on filter design on Vivado 2017.4. I'm using DDS for generating sine wave and giving it to FIR compiler .

When I tried simulating , I'm getting the error which I'm attaching in the snapshot below.

Can u please help me out in solving this error.

 

sim_error.PNG

Thanks and regards,

Akshay M

sim_error.PNG
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13 Replies
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Moderator
Moderator
5,349 Views
Registered: ‎09-15-2016

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

Hi @akshay_iyngr95

 

Please share the project or test case to look into this further. Also try in latest tool version 2018.1 once.

 

Regards

Rohit

Regards
Rohit
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Moderator
Moderator
5,343 Views
Registered: ‎09-15-2016

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

Hi @akshay_iyngr95,

 

Can you please check if the following posts helps:

https://forums.xilinx.com/t5/Simulation-and-Verification/vivado-2015-1-simulation-error-Failure-ERROR-add-1-must-be-in/td-p/600653

https://forums.xilinx.com/t5/Simulation-and-Verification/vivado-simulation-block-memory-module-failure/td-p/646336

 

Thanks & Regards,
Sravanthi B

Thanks & Regards,
Sravanthi B
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Participant
Participant
5,331 Views
Registered: ‎02-19-2018

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

Hi, @bandi

 

I tried changing the clock stimulus but it didn't work.

The valid signal to fir compiler is given from dds compiler and the files are encrypted in IP.

I'll be sharing the project files soon.

 

Thanks and regards,

Akshay M 

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Participant
Participant
5,330 Views
Registered: ‎02-19-2018

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

Hi, @thakurr

 

I'll be sharing the project files soon.

 

Thanks and regards,

Akshay M

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Participant
Participant
5,310 Views
Registered: ‎02-19-2018

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

Hi, @thakurr

I'm attaching my project tar file below. please have a look into it.

 

Thanks and regards,

Akshay M

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Moderator
Moderator
5,290 Views
Registered: ‎05-31-2017

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

Hi @akshay_iyngr95,

 

File test_design_fir.v is missing from the shared project. Because of the missing file we can't move further. So, can you please share the complete archived project. To archive the project click on File --> Archive Project in Vivado

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Participant
Participant
5,286 Views
Registered: ‎02-19-2018

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

Hi, @shameera

Sorry for that.

I'm attaching the archived files of my project below.

 

 

Thanks and regards,

Akshay M

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Xilinx Employee
Xilinx Employee
5,268 Views
Registered: ‎07-16-2008

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

It looks the M_AXIS_PHASE_0_tready is not initialized.

I tried to assign an initial value to it in the testbench and the error was not seen.

wire  M_AXIS_PHASE_0_tready = 1'b1;

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Adventurer
Adventurer
2,521 Views
Registered: ‎01-27-2008

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

@graces 

Interesting. Is there a way for Xilinx to make that error traceable? I was able to quickly resolve through this thread, but the error itself can't be traced. I found it after I added tready to an axis interface and forgot to hook it up.  Same error.

Thanks for the post providing a quick solution.

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Xilinx Employee
Xilinx Employee
2,506 Views
Registered: ‎07-16-2008

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

The error message is coming from the assertion in AXI SRL FIFO (encrypted) used within the IP core. 
 
This kind of failure is typically seen when master and slave AXI are not initialized. e.g. when the slave TVALID and TDATA are in an 'U' or 'X' state.
The unknown or undefined state applied to the core cause the assertions in the AXI SRL FIFO to be triggered, which terminates the simulation.
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Adventurer
Adventurer
2,497 Views
Registered: ‎01-27-2008

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

@graces 

Yes I understand where it came from, and it was clear from your analalysis of the OP's code how to correct the simulation failure. All I am saying is that this simulation failure didn't trace to an obvious and simple solution. I ask that Xilinx considering providing the traceability to ease debug.

 

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Xilinx Employee
Xilinx Employee
2,491 Views
Registered: ‎07-16-2008

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

The IP source is encrypted and therefore not traceable.

We can document an answer though, to provide the solution to this error and avoid duplicate effort.

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Adventurer
Adventurer
2,473 Views
Registered: ‎01-27-2008

Re: ERROR:add_1 must be in range [-1,DEPTH-1]

Ah ok, I didn't know why it was not a traceable simulation failure. Understood, thanks.

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