03-12-2009 05:32 AM
Hello, Im an IT engineer student and I'm taking a course on designing simple combinational and secuencial circuits. My problem comes in when I'm done creating the schematics of a simple circuit and try to create the test bench. I have installed ModelSim with its licence.dat file. The error I'm getting is the following:
tarted : "Creating Tbw file".
ERROR:HDLParsers:3562 - pepExtractor.prj line 1 Expecting 'vhdl' or 'verilog' keyword, found 'work'.
Compiling vhdl file "C:/Documents and Settings/Administrator/Desktop/Practica1/Pr11.vhf" in Library work.
ERROR:HDLParsers:164 - "C:/Documents and Settings/Administrator/Desktop/Practica1/Pr11.vhf" Line 29. parse error, unexpected CLOSEPAR, expecting IDENTIFIER
WARNING:HDLParsers:3481 - Library work has no units. Did not save reference file "C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/xil_2256_34/hdllib.ref" for it.
What am I doing wrong or missing?
03-14-2009 06:55 AM
03-12-2009 05:44 PM
Check out this thread and its solution as the problem appears to be similar to yours:
Also, please refrain from creating projects in locations where its directory path contains spaces.
03-13-2009 04:49 AM
03-13-2009 10:01 AM
Try the following:
1) In the Sources pane, click on the "Files" tab ("Library" tab if using a version other than 10.1). See if the testbench waveform file is listed.
If yes, right-click on it and remove it.
If no, proceed forward
2) Run "Clean Up Project Files" from the Project Menu. Try "adding new source --> Testbench waveform" again
3) If all else fails, create a new project with your sources.
Hope this helps.
03-14-2009 06:45 AM
"Now when I had the TestBench source file it saids creating file but it never does add the file."
This often means the VHDL source file you want to test, has a syntax error, so the testbench creator can't parse it.
Try a syntax check on it, or ewen synthesis. If that works, try the testbench generator again.
03-14-2009 06:55 AM