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Error during Elaboration in NCSIM

Visitor
Posts: 9
Registered: ‎10-19-2011

Error during Elaboration in NCSIM

My design compilation completed succesfully.

It is using the Xilinx Library files i have provided the path of the secureip for GTX Wrapper.

 

During the state of elaboration i have *E,DUPTOP and following error message.

*E,CUVMUR related to srio.v.

 

I am trying to simulate the Xilinx example design SRIO for Kintex-7.

 

Thanks for your time.

 

 

Xilinx Employee
Posts: 3,051
Registered: ‎10-24-2013

Re: Error during Elaboration in NCSIM

Hi,
Please post the complete error message given by tool.
Thanks,Vijay
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Visitor
Posts: 9
Registered: ‎10-19-2011

Re: Error during Elaboration in NCSIM

ncelab: *F,DUPTOP: duplicate top-level unit names:

ncverilog: *E,ELBERR: Error during elaboration (status 2), exiting.

 

This is error message i am using the single step script with cds.lib and hdl.var for the library mapping compiled with compxlib.

Xilinx Employee
Posts: 3,785
Registered: ‎04-16-2012

Re: Error during Elaboration in NCSIM

Hi,

Attach your simulation script here.

Thanks
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Visitor
Posts: 9
Registered: ‎10-19-2011

Re: Error during Elaboration in NCSIM

Please find the below script and related files which i have used for the simulation.

 

 

#script.sh

----------------------------------------------------------------------------------------------------------------------------------------------------------------

#!/bin/sh

rm -rf ./INCA_libs/*
ncverilog -y $XILINX/verilog/src/unisims\
/tools/ISE_DS/ISE/secureip/ncsim/gtxe2_channel_ncsim/gtxe2_channel_001.vp\
/tools/ISE_DS/ISE/secureip/ncsim/gtxe2_channel_ncsim/gtxe2_channel_002.vp\
/tools/ISE_DS/ISE/secureip/ncsim/gtxe2_common_ncsim/gtxe2_common_001.vp\
/tools/ISE_DS/ISE/secureip/ncsim/gtxe2_common_ncsim/gtxe2_common_002.vp\
-timescale 1ns/1ps\
+incdir+$XILINX/verilog/src +libext+.v $XILINX/verilog/src/glbl.v\
-f vfile.f -64bit

----------------------------------------------------------------------------------------------------------------------------------------------------------------

vfile.f contains the compilation files form the xilinx IP generated files.

 

 

#cds.lib

----------------------------------------------------------------------------------------------------------------------------------------------------------------

INCLUDE /cad/cadence/INCISIV12.10.007/tools.lnx86/inca/files/cds.lib
define worklib ./worklib
define ip_lib ./ip.lib
DEFINE secureip /tools/14.4/ISE_DS/ISE/verilog/ncsim/10.20-s119/lin64/secureip
DEFINE unimacro /tools/14.4/ISE_DS/ISE/vhdl/ncsim/10.20-s119/lin64/unimacro
DEFINE unisim /tools/14.4/ISE_DS/ISE/vhdl/ncsim/10.20-s119/lin64/unisim
DEFINE unisims_ver /tools/14.4/ISE_DS/ISE/verilog/ncsim/10.20-s119/lin64/unisims_ver
DEFINE unimacro_ver /tools/14.4/ISE_DS/ISE/verilog/ncsim/10.20-s119/lin64/unimacro_ver
DEFINE simprim /tools/14.4/ISE_DS/ISE/vhdl/ncsim/10.20-s119/lin64/simprim
DEFINE simprims_ver /tools/14.4/ISE_DS/ISE/verilog/ncsim/10.20-s119/lin64/simprims_ver
DEFINE xilinxcorelib /tools/14.4/ISE_DS/ISE/vhdl/ncsim/10.20-s119/lin64/xilinxcorelib
DEFINE xilinxcorelib_ver /tools/14.4/ISE_DS/ISE/verilog/ncsim/10.20-s119/lin64/xilinxcorelib_ver

----------------------------------------------------------------------------------------------------------------------------------------------------------------

#hdl.var

define verilog_suffix ( .v, .vr, .vb, .vg )
define vhdl_suffix ( .vhd, .vhdl )

define LIB_MAP ($XILINX/verilog/src=> ip_lib, + => worklib )

----------------------------------------------------------------------------------------------------------------------------------------------------------------

 

 

Xilinx Employee
Posts: 1,304
Registered: ‎07-16-2008

Re: Error during Elaboration in NCSIM

Please refer to the following AR on simulating secureip design with Vivado.

http://www.xilinx.com/support/answers/31060.htm

 

If you have compiled simulation libraries with Compxlib, you can reference the libraries with -libname switch in ncelab command without compiling the .vp.

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