05-09-2019 09:00 AM
In our project we are using Sparton 6 FPGA with external 128K X 8 bit CMOS SRAM.
I am new to VHDL coding, i don't know how to write Test bench to this implementation
please share if any related links and code to referer
Could anyone give me suggestions?
Thanks a lot!
05-09-2019 10:13 AM
Many commercial RAMs have simulation models available. Have you searched the manufacturer's for a simulation model?
05-13-2019 03:48 AM
SRAMs are fairly simple. It shouldnt be hard to create your own model using the datasheet.
05-13-2019 06:07 PM
You can probably google around and find some direct examples. Here's one such example for a SRAM and testbench in VHDL.
You can also pull SRAM that is similar to the one you have to model. Ensure that it's similar in the bus interface and you should be (mostly) good.
For instance, Cypress provides models: Here's several models: