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Visitor
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Registered: ‎10-04-2018

FATAL_ERROR occurs when simulating the ddr4_model.sv provided by Xilinx

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I've attached an image containing the full error message that is being outputted in the consoel. In addition, I've also attached the xsimcrash.log pertaining to the error. While I can't pinpoint the exact cause of the error I am convinced DDR4 model is involved because when I disable the model, the simulation runs fine. The error is repeatable and occurs at approximately the same time despite changing a variety of simulation options. However, I was able to get the simulation to continue pass this point when I changed the simulation setting xsim.elaborate.debug_level to "off" (which, is found under the Elabration tab). Unfortunately this prevents any waveform signals from being generated and thus makes the simulation much less useful. Any other changes to the settings didn't seem to affect the failure other than changing when it happens by a few nanoseconds. If anyone has any suggestions they would be greatly appreciated. Thank you in advance.

fatal_error.PNG
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Visitor
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Registered: ‎10-04-2018

During the time I posted this solution I was running Vivado on CentOS 7, which the solution is valid for.  However, since then I've also had an oppurtunity to try it on Windows 10 and the error still persists.  I just figured I would give an update in case anyone else was having a similar issue.

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Moderator
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Registered: ‎09-15-2016

Hi @dionhicks ,

Which version of Vivado are you using and on which OS? Can you please share the archived project to check this issue at our end.

Thanks & Regards,
Sravanthi B
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Visitor
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Registered: ‎10-04-2018

Thanks for the reply!  Unfortunately I won't be able send the project due to its sensitive nature.  The version of Vivado I'm using is 2018.3 and the OS is CentOS 7.  I've also ran the simulation on Windows 7 with the same Vivado version and obtained an error message which I've attached.  On the Windows machine it actually crashes much earlier and mentions the ddr4_model.sv as the cause of the error.

windows_error.png
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Visitor
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Registered: ‎10-04-2018

After doing some more digging I found a solution to the issue.  Contained within the testbnech file provided by the example project there where primitives with the label of "tran" which apparently are not supported by the Xlinix Simulator.  They are part of a 'ifdef block based on the Xilinx Simulator but for some reason were still being included in the project.  After commenting out all of the "tran" logic the simulator crash went away.  Below is a snippet of the code fix:

for (r = 0; r < RANK_WIDTH; r++) begin:tranDQ2
        for (i = 0; i < NUM_PHYSICAL_PARTS; i++) begin:tranDQ12
          for (s = 0; s < 8; s++) begin:tranDQ2
         //  `ifdef XILINX_SIMULATOR
           short bidiDQ(iDDR4[(r*NUM_PHYSICAL_PARTS)+i].DQ[s], c0_ddr4_dq[s+i*8]);
//           `else
//            tran bidiDQ(iDDR4[(r*NUM_PHYSICAL_PARTS)+i].DQ[s], c0_ddr4_dq[s+i*8]);
//           `endif
          end
        end
      end

      for (r = 0; r < RANK_WIDTH; r++) begin:tranDQS2
        for (i = 0; i < NUM_PHYSICAL_PARTS; i++) begin:tranDQS12
      //  `ifdef XILINX_SIMULATOR
          short bidiDQS(iDDR4[(r*NUM_PHYSICAL_PARTS)+i].DQS_t, c0_ddr4_dqs_t[i]);
          short bidiDQS_(iDDR4[(r*NUM_PHYSICAL_PARTS)+i].DQS_c, c0_ddr4_dqs_c[i]);
          short bidiDM(iDDR4[(r*NUM_PHYSICAL_PARTS)+i].DM_n, c0_ddr4_dm_dbi_n[i]);
//        `else
//          tran bidiDQS(iDDR4[(r*NUM_PHYSICAL_PARTS)+i].DQS_t, c0_ddr4_dqs_t[i]);
//          tran bidiDQS_(iDDR4[(r*NUM_PHYSICAL_PARTS)+i].DQS_c, c0_ddr4_dqs_c[i]);
//          tran bidiDM(iDDR4[(r*NUM_PHYSICAL_PARTS)+i].DM_n, c0_ddr4_dm_dbi_n[i]);
//        `endif
        end
      end
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Visitor
Visitor
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Registered: ‎10-04-2018

During the time I posted this solution I was running Vivado on CentOS 7, which the solution is valid for.  However, since then I've also had an oppurtunity to try it on Windows 10 and the error still persists.  I just figured I would give an update in case anyone else was having a similar issue.

View solution in original post

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