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sraza

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05-15-2012 07:16 AM

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Registered:
03-13-2012

FFT simulation verification Problem

Dear all,

I have design fixed point fft using Logic core and using XIlinx ISE.

I have given to FFT several uniform data, different patterns of data like...32,16,32,16,32,16....

and I have verified the result through Matlab. **They are correct.**

but when it comes to give** sine wave signa**l. It is a real head ache.** I have been trying for more than1 week**

1) I first produce sine wave signal on Matlab. since it is in floaing point, I converted it into 20 wordlength fixed point

with 1-1-18 as sign-integer-decimal number format...

2) then I copy this binary data to a text file and call through my verilog simulataion...So then feed this Sine wave's binary format to FFT core....

Now I am not getting the result which can be verified through Matlab...

I have tried every thing possible which I can do so now I need some help....**:|**

I can give other details as well if all these are incomplete...

By the way I cannot find that fixed point fft has how many bits for integer and how many for fraction...

Regards,

Shan

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rcingham

Teacher

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05-15-2012 08:08 AM

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Registered:
09-09-2010

Are we supposed to guess the difference, or will you just tell us?

BTW, is the period of the sinewave a submultiple of the FFT length?

------------------------------------------

"If it don't work in simulation, it won't work on the board."

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bwiec

Xilinx Employee

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05-15-2012 08:20 AM

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Registered:
08-02-2011

Hi Shan,

As rcingham mentioned, it will be much easier for us to help if you provide some more info about your system and test setup. Preferably data (screenshots, code, simulation info, core configuration info, etc).

If you're not getting correct data on the output, the next step would be to back up and check your input to the core. See if you're even *applying* the data you expect.

By the way I cannot find that fixed point fft has how many bits for integer and how many for fraction...

From the FFT datasheet:

"Note that the core does not have a specific location for the binary point. The output simply

maintains the same binary point location as the input."

www.xilinx.com

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sraza

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05-17-2012 01:16 AM

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Registered:
03-13-2012

Dear Thank you for your response and sorry for delay,

was busy with assignments

Well

1) My FFT core takes 64 chunks of data at a time

2) Fixed point with 20 bit input (only real part, imaginary input =0)

3) output is Unscaled (since I did not understand scaling,if any good material then I'll be thankfull)

4) output is 27 bit.

Well I don't know what frequency to give into the core, but in actual Matlab program I generated 200 Hz wave and get the result, which later I imported to Verilog Test bench... I have just a feeling why I am getting different results from Matlab and Verilog, which discuss in the End of this meail (sorry)

Following is the result that I am getting from my FFT core and output is imported to Matlab and drawn as below...

**"If you're not getting correct data on the output, the next step would be to back up and check your input to the core. See if you're even applying the data you expect."**

Done this above step, input is all good at input core...!

Well,

1) I think I have taken 64 chunks of data each time, that splits the data may be this has caused the erroe

2) I have fixed point input but do not

**NOTE: Please remember that when I give some fixed pattern of data of constant data, I get the correct result as verified by Matlab as well, but of course in real world we do not have constant or repeateted data**

Best Regards and thanks

Shan

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rcingham

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05-17-2012 02:42 AM

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Registered:
09-09-2010

------------------------------------------

"If it don't work in simulation, it won't work on the board."

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thomas1974

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05-18-2012 03:51 PM

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Registered:
05-16-2012

is it possible that you used only one part of the FFT core output? (maybe real only)?

The values seem to be somehow negative in the display. Also some freqs seem to be missing (see the symmetry).

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